Si recess method in HKMG replacement gate technology
The present disclosure relates to a method of embedding an ESF3 memory in a HKMG integrated circuit that utilizes a replacement gate technology. The ESF3 memory is formed over a recessed substrate which prevents damage of the memory control gates during the CMP process performed on the ILD layer. An asymmetric isolation zone is also formed in the transition region between the memory cell and the periphery circuit boundary.
1. A method of forming an integrated circuit comprising:
providing a substrate with a planar top surface;
recessing a section of the substrate to a depth below the planar top surface to form recessed and un-recessed surfaces that are disposed horizontally on the substrate;
forming a pair of memory cells including a pair of gate electrodes over the recessed surface; and
forming a high-k metal gate (HKMG) circuitry including a HKMG gate electrode over the un-recessed surface;
wherein an upper surface of at least one of the pair of gate electrodes is co-planar with an upper surface of the HKMG gate electrode.
2. The method of claim 1 , further comprising forming a transition region between the recessed and the un-recessed surfaces that extends into the substrate, having an asymmetrical geometry along an axis that is perpendicular to the planar top surface of the substrate.
3. The method of claim 1 , wherein:
the memory cells comprise a pair of control gates;
the HKMG circuitry comprises a sacrificial gate; and
top surfaces of the pair of control gates and the sacrificial gate are co-planar.
4. The method of claim 3 , wherein forming the HKMG circuitry comprises a chemical mechanical polishing (CMP) process that stops at the top surfaces of the sacrificial gate as well as the pair of control gates.
5. The method of claim 1 , wherein the depth of the recessed surface ranges from approximately 150 Angstroms to 800 Angstroms.
6. A method of forming an integrated circuit comprising:
providing a silicon (Si) substrate with a planar top surface;
recessing a section of the Si substrate to a depth below the planar top surface to form a recessed surface on the Si substrate;
forming active regions separated by isolation zones within the Si substrate;
forming a memory cell, which includes a control gate, over the recessed surface;
forming a sacrificial gate over the planar top surface;
forming an inter-layer dielectric (ILD) layer over the memory cell and sacrificial gate; and
performing a chemical mechanical polishing (CMP) operation on the ILD layer, wherein the CMP operation stops to define top surfaces of the control gate and the sacrificial gate.
7. The method of claim 6 , wherein a first isolation zone formed in the recessed surface and a second isolation zone formed in the planar top surface have symmetric geometries along an axis that is perpendicular to the planar top surface of the Si substrate and a third isolation zone formed in a transition region between the recessed and the planar top surfaces has an asymmetric geometry along the axis.
8. The method of claim 6 , wherein recessing the section of the Si substrate comprises:
covering a portion of the planar top surface of the Si substrate with a mask while leaving the section of the Si substrate which is to be recessed exposed;
selectively growing an oxide on the exposed section of the Si substrate through wet oxidation without growing the oxide on the portion of the planar top surface covered by the mask; and
performing a first etch to selectively remove the oxide grown on the exposed section of the Si substrate to establish the recessed surface.
9. The method of claim 8 , wherein the first etch comprises a combination of dry etch and wet etch or a wet etch only.
10. The method of claim 6 , wherein recessing the section of the Si substrate comprises:
covering a portion of the planar top surface of the Si substrate while leaving the section of the Si substrate which is to be recessed exposed;
dry etching the exposed section of the Si substrate to form the recessed surface.
11. The method of claim 6 , wherein forming active regions separated by isolation zones comprises:
depositing a silicon nitride (SiN) layer over the planar top surface of the Si substrate;
forming a mask over the SiN layer, the mask covering some portions of the SiN layer while leaving other portions of the SiN layer exposed;
performing a dry etch to remove the exposed portions of the SiN layer and corresponding Si material underneath, thereby leaving an isolation trench in the Si substrate;
depositing an STI (shallow trench isolation) oxide in the isolation trench over the Si substrate;
polishing and leveling a step height of the STI oxide; and
removing the SiN layer from the Si substrate.
12. The method of claim 6 , wherein forming a memory cell comprises:
forming source and drain regions in the active regions;
forming a pair of control gate structures comprising a thicker control gate over a wider yet thinner floating gate;
forming an erase gate between two adjacent control gate structures;
forming select gates on opposing sides of two adjacent control gate structures; and
forming a dielectric layer between the gates of the memory cells.
13. The method of claim 6 , further comprising forming a HKMG transistor by performing the following acts:
prior to forming the sacrificial gate, forming a high-k dielectric layer over the planar top surface of the Si substrate;
forming a metal etch-stopping layer over the high-k dielectric layer;
forming a sacrificial polysilicon layer over the metal etch-stopping layer;
patterning the sacrificial polysilicon layer to form the sacrificial gate;
forming the ILD layer over the memory cell and the sacrificial gate;
performing the chemical mechanical polishing (CMP) on the ILD layer to expose the top surface of the sacrificial polysilicon layer;
performing an etch while the top surface of the sacrificial polysilicon layer is exposed to selectively remove the sacrificial polysilicon layer, thereby forming an opening; and
forming a metal gate electrode in the opening, thereby forming the high-k metal gate (HKMG) transistor.
14. A method, comprising:
providing a semiconductor substrate which includes a memory region and a logic region, wherein an upper surface of the memory region is co-planar with an upper surface of the logic region;
forming a conformal dielectric layer over the upper surface of the memory region and over the upper surface of the logic region;
selectively removing the conformal dielectric layer from over the memory region to expose the upper surface of the memory region while leaving the upper surface of the logic region covered by the conformal dielectric layer;
with the conformal dielectric layer in place over the logic region, selectively forming an oxide which extends into the exposed upper surface of the memory region to a depth that is lower than a lower surface of the conformal dielectric layer;
selectively removing the oxide from the memory region to provide the memory region with a recessed upper surface that is recessed relative to the upper surface of the logic region;
forming a high-k-metal gate (HKMG) transistor over the upper surface of the logic region; and
forming a memory cell over the recessed upper surface of the memory region.
15. The method of claim 14 , wherein the memory cell includes a control gate and the HKMG transistor includes a gate electrode, wherein an upper surface of the control gate is co-planar with an upper surface of the gate electrode.
16. The method of claim 14 , wherein the oxide is selectively formed by a wet oxidation process.
17. The method of claim 14 , wherein the memory cell is a split gate flash memory cell, and at least a portion of a floating gate of the split gate flash memory cell is at a height below that of the upper surface of the logic region.
18. The method of claim 14 , further comprising:
forming an isolation trench in the substrate to separate the memory region from the logic region, wherein the isolation trench has a lower surface which extends below the recessed upper surface of the memory region;
filling the isolation trench with a dielectric to provide electrical isolation between the memory region and logic region.
19. The method of claim 14 , wherein forming the HKMG transistor and forming memory cell comprises:
forming a memory control gate over the recessed upper surface in the memory region;
forming a sacrificial gate over the upper surface of the logic region;
forming sidewall spacers about the sacrificial gate;
forming an inter-layer dielectric (ILD) layer over the memory control gate, sidewall spacers, and sacrificial gate;
performing a chemical mechanical polishing (CMP) operation on the ILD layer to establish an upper surface of the memory control gate and an upper surface for the sacrificial gate which are co-planar with one another.
20. The method of claim 19 , further comprising:
after the CMP operation, removing the sacrificial gate to leave a recess between the sidewall spacers;
filling the recess with a replacement metal gate.