IP Library Granted Patent US 9,608,521
Granted Patent B2
US 9,608,521 · App. 14/643,743 · Granted Mar 28, 2017

DC/DC converter activation stability control

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,608,521
App. No.
14/643,743
Granted
Mar 28, 2017
Kind
B2
Abstract

Provided is a DC/DC converter capable of operating a circuit to perform stable control even when an output voltage becomes 0 V at the time of activation of a power supply voltage or due to a load short circuit. The DC/DC converter includes an ON-timer circuit including: a ripple generation circuit configured to generate and output a ripple component based on a control signal; an averaging circuit configured to output a signal obtained by averaging an output of the ripple generation circuit; a timer circuit configured to generate and output an ON-time signal based on the signal of the averaging circuit and the control signal; and an activation circuit configured to increase a voltage of an output terminal of the ripple generation circuit to a predetermined voltage.

Claims (26)

1. A DC/DC converter, comprising:

a first comparator configured to output a result of comparison between a first sum voltage at inverting inputs, obtained by adding a first output voltage of a pseudo ripple component and a divided output voltage of the DC/DC converter, and a second sum voltage at non-inverting inputs, obtained by adding a second output voltage of the pseudo ripple component and a reference voltage;

an ON-timer circuit configured to receive a control signal from an output port of a Reset/Set (RS) flip-flop circuit, the control signal inputs to a drive circuit which controls a gate of one or more output transistor, and the ON-timer circuit outputs an ON-time signal to a R input port of the RS flip-flop circuit, wherein a S input port of the RS flip-flop circuit receives the output result of comparison from the first comparator, wherein the output port of the RS flip-flop circuit outputs the control signal which is synchronized to both the input of the ON-timer circuit and to the drive circuit for controlling the one or more output transistor;

the ON-timer circuit comprising:

a ripple generation circuit configured to generate and output a ripple component based on the control signal received at the input of the ON-timer circuit;

an averaging circuit configured to output a signal obtained by averaging the outputted ripple component of the ripple generation circuit to form a predetermined voltage which is proportional to the output voltage of the DC/DC converter;

a timer circuit configured to generate and output the ON-time signal based on the signal of the averaging circuit and the control signal; and

an activation circuit configured to generate and output the ON-time signal based on the signal of the averaging circuit configured to generate and output the ON-time signal based on the signal of the averaging circuit and the control signal; and

an activation circuit configured to increase a voltage of an output terminal of the ripple generation circuit to the predetermined voltage such that the timer circuit operates without directly using the output voltage of the DC/DC converter to achieve activation stability control in the DC/DC converter.

2. The DC/DC converter according to claim 1 , wherein the activation circuit comprises:

a first current source;

a first transistor including a gate and a drain that are connected to the first current source; and

a second transistor including a gate connected to the gate of the first transistor and a source connected to the output terminal of the ripple generation circuit, the second transistor being configured to cause a current to flow to the output terminal of the ripple generation circuit until the output terminal of the ripple generation circuit has reached the predetermined voltage.

3. The DC/DC converter according to claim 1 , wherein the activation circuit comprises:

a first transistor including a source connected to the output terminal of the ripple generation circuit, the first transistor being configured to cause a current to flow to the output terminal of the ripple generation circuit until the output terminal of the ripple generation circuit has reached the predetermined voltage;

a pull-up element connected to a gate of the first transistor; and

a second transistor including a gate connected to the output terminal of the ripple generation circuit and a drain connected to the gate of the first transistor.

4. The DC/DC converter according to claim 1 , wherein the activation circuit comprises:

a first transistor including a source connected to the output terminal of the ripple generation circuit, the first transistor being configured to cause a current to flow to the output terminal of the ripple generation circuit until the output terminal of the ripple generation circuit has reached the predetermined voltage; and

a constant voltage circuit connected to a gate of the first transistor.

5. The DC/DC converter according to claim 1 , wherein the ripple generation circuit comprises:

a second current source;

a switch circuit including one terminal connected to the second current source, and configured to be controlled by the control signal;

a capacitor connected to another terminal of the switch circuit; and

an impedance element connected to said another terminal of the switch circuit.

6. The DC/DC converter according to claim 1 , wherein the voltage corresponding to the output voltage, which is input to the first comparator, comprises an output voltage of the averaging circuit.

Assignments (5)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 037783 FRAME: 0166. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 23, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 037903/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION .
Reel/Frame 037783/0166 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2015
From: SHIINA, YOSHIOMI; UNO, MASAYUKI
To: SEIKO INSTRUMENTS INC.
Reel/Frame 035143/0561 →