IP Library Granted Patent US 9,627,401
Granted Patent B2
US 9,627,401 · App. 14/639,084 · Granted Apr 18, 2017

Method for manufacturing semiconductor memory device and semiconductor memory device

Inventors: Hirotaka Tsuda (Tokyo, JP); Yusuke Oshiki (Mie, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L27/11582H01L21/0217H01L21/02164H01L21/31111H01L21/31116H01L27/11565
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Quick Facts
Patent No.
US 9,627,401
App. No.
14/639,084
Granted
Apr 18, 2017
Kind
B2
Abstract

According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.

Claims (55)

1. A semiconductor memory device comprising:

a stacked body including a plurality of electrode layers stacked with insulators interposed between the electrode layers;

a columnar portion penetrating in the stacked body in a stacking direction of the stacked body, the columnar portion including a semiconductor film extending in the stacking direction, and a cylindrical film provided between the electrode layers and the semiconductor film; and

a separation portion extending in the stacking direction and in a first direction intersecting the stacking direction and separating the stacked body into a first portion and a second portion of the stacked body in a second direction intersecting the stacking direction and the first direction, the separation portion being disposed between the first portion and the second portion of the stacked body, the first portion and the second portion having a pair of sidewalls facing each other with the separation portion interposed, a width in the second direction between the pair of sidewalls being larger than a diameter of the columnar portion,

the sidewalls having shapes in which a plurality of concave portions are disposed in the first direction, the plurality of concave portions being arranged periodically in the first direction.

2. The device according to claim 1 , wherein the plurality of concave portions have curvature.

3. The device according to claim 1 , wherein the separation portion includes:

a conductive layer; and

an insulating film provided between the electrode layers and the conductive layer.

4. The device according to claim 3 , further comprising a substrate provided below the stacked body, a lower end of the semiconductor film and a lower end of the conductive layer being in contact with the substrate,

wherein the semiconductor film and the conductive layer are electrically connected to each other through the substrate.

5. The device according to claim 1 , wherein

the columnar portion includes a plurality of first columnar portions and a plurality of second columnar portions, the plurality of first columnar portions being provided in the first portion of the stacked body and adjacent to the separation portion, the plurality of second columnar portions being provided in the second portion of the stacked body and adjacent to the separation portion, and

the plurality of concave portions are arranged in the first direction in a same pitch as the plurality of first columnar portions and the plurality of second columnar portions both arranged in the first direction.

6. The device according to claim 1 , wherein the sidewalls have shapes in which each of the plurality of concave portions extends in the stacking direction.

7. The device according to claim 1 , wherein a plurality of the columnar portions are arranged in a staggered arrangement in the stacked body.

8. The device according to claim 7 , wherein

the sidewalls include a sidewall on the first portion side and a sidewall on the second portion side,

the plurality of concave portions are disposed on each of the sidewall on the first portion side and the sidewall on the second portion side.

9. The device according to claim 8 , wherein the sidewall on the first portion side and the sidewall on the second portion side have shapes in which the plurality of concave portions are disposed at different positions from each other in the first direction.

10. The device according to claim 9 , wherein

the columnar portion includes a plurality of first columnar portions and a plurality of second columnar portions, the plurality of first columnar portions being arranged in the first direction adjacent to the separation portion in the first portion of the stacked body, the plurality of second columnar portions being arranged in the first direction adjacent to the separation portion in the second portion of the stacked body,

the plurality of first columnar portions are arranged in a position relationship with a half pitch shifted in the first direction from a plurality of first concave portions disposed at the sidewall on the first portion side,

the plurality of second columnar portions are arranged in a position relationship with a half pitch shifted in the first direction from a plurality of second concave portions disposed at the sidewall on the second portion side.

11. The device according to claim 10 , wherein

the plurality of first concave portions are arranged at positions corresponding to the plurality of second columnar portions in the first direction,

the plurality of second concave portions are arranged at positions corresponding to the plurality of first columnar portions in the first direction.

12. A semiconductor memory device comprising:

a stacked body including a plurality of electrode layers stacked with insulators interposed between the electrode layers;

a plurality of columnar portions arranged in a staggered arrangement so as to penetrate in the stacked body in a stacking direction of the stacked body, each of the plurality of columnar portions including a semiconductor film extending in the stacking direction, and a cylindrical film provided between the electrode layers and the semiconductor film; and

a separation portion extending in the stacking direction and in a first direction intersecting the stacking direction, and separating the stacked body into a first portion and a second portion of the stacked body in a second direction intersecting the stacking direction and the first direction, the separation portion being disposed between the first portion and the second portion of the stacked body so that the first portion and the second portion have a pair of sidewalls facing each other with the separation portion interposed,

the pair of sidewalls including a sidewall on the first portion side and a sidewall on the second portion side,

a plurality of first concave portions being disposed at the sidewall on the first portion side along the first direction, a plurality of second concave portions being disposed at the sidewall on the second portion side along the first direction,

positions in the first direction of the plurality of first concave portions being shifted from positions in the first direction of the plurality of second concave portions.

13. The device according to claim 12 , wherein

the plurality of columnar portions include a plurality of first columnar portions and a plurality of second columnar portions, the plurality of first columnar portions being arranged in the first direction adjacent to the separation portion in the first portion of the stacked body, the plurality of second columnar portions being arranged in the first direction adjacent to the separation portion in the second portion of the stacked body,

the plurality of first columnar portions are arranged in a position relationship with a half pitch shifted in the first direction from the plurality of first concave portions disposed at the sidewall on the first portion side,

the plurality of second columnar portions are arranged in a position relationship with a half pitch shifted in the first direction from the plurality of second concave portions disposed at the sidewall on the second portion side.

14. The device according to claim 13 , wherein

the plurality of first concave portions are arranged at positions corresponding to the plurality of second columnar portions in the first direction,

the plurality of second concave portions are arranged at positions corresponding to the plurality of first columnar portions in the first direction.

15. The device according to claim 12 , wherein the plurality of first concave portions and the plurality of second concave portions have curvature.

16. The device according to claim 1 , wherein the plurality of concave portions are disposed at the plurality of electrode layers of the first portion and the second portion of the stacked body.

17. The device according to claim 12 , wherein the plurality of first concave portions are disposed at the plurality of electrode layers of the first portion of the stacked body, and the plurality of second concave portions are disposed at the plurality of electrode layers of the second portion of the stacked body.

18. The device according to claim 1 , wherein the pair of sidewalls includes a sidewall on the first portion side and a sidewall on the second portion side, and positions in the first direction of the plurality of concave portions disposed at the sidewall on the first portion side are shifted with a half pitch from positions in the first direction of the plurality of concave portions disposed at the sidewall on the second portion side.

19. The device according to claim 12 , wherein

the plurality of first concave portions and the plurality of second concave portions are arranged periodically in the first direction, and

the positions in the first direction of the plurality of first concave portions are shifted with a half pitch from the positions in the first direction of the plurality of second concave portions.

20. A semiconductor memory device comprising:

a stacked body including a plurality of electrode layers stacked with insulators interposed between the electrode layers;

a plurality of columnar portions arranged in a staggered arrangement so as to penetrate in the stacked body in a stacking direction of the stacked body, each of the plurality of columnar portions including a semiconductor film extending in the stacking direction, and a cylindrical film provided between the electrode layers and the semiconductor film; and

a separation portion extending in the stacking direction and in a first direction intersecting the stacking direction, and separating the stacked body into a first portion and a second portion of the stacked body in a second direction intersecting the stacking direction and the first direction, the separation portion being disposed between the first portion and the second portion of the stacked body so that the first portion and the second portion have a pair of sidewalls facing each other with the separation portion interposed,

the pair of sidewalls including a sidewall on the first portion side and a sidewall on the second portion side,

a plurality of first concave portions being disposed at the sidewall on the first portion side along the first direction, a plurality of second concave portions being disposed at the sidewall on the second portion side along the first direction,

the plurality of first concave portions and the plurality of second concave portions having asymmetric positional relationship in the first direction with respect to a central axis of the separation portion along the first direction.

Assignments (6)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE POSTAL CODE PREVIOUSLY RECORDED ON REEL 042910 FRAME 0321. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043747/0290 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 042910/0321 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2015
From: TSUDA, HIROTAKA; OSHIKI, YUSUKE
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 035516/0407 →
Priority Claims (1)
JP 2014-221032 · Oct 30, 2014 · national
Continuity (1)
Related Publication 20160126252A1 · May 5, 2016