Host-managed non-volatile memory

1. An apparatus comprising:

a processor;

a chipset;

a memory; and

indirection logic to:

receive a host logical block address (LBA) associated with a first sector of data,

map the host LBA from a host address space to a first device LBA in a device address space, the device address space related to a non-volatile memory (NVM) storage device physical memory address space, and

provide the first sector of data and the first device LBA to the NVM storage device; wherein:

the device address space comprises metadata, a transaction log, and a data portion;

the data portion comprises a free list, a plurality of index nodes, a plurality of leaf nodes and a plurality of extents; and

the indirection logic is further to allocate a leaf node and an extent from the free list, the extent corresponding to the first sector of data.

2. The apparatus of claim 1 , wherein the indirection logic is further to write the host LBA, the first device LBA and a length corresponding to the first sector of data to the leaf node.

3. The apparatus claim 1 , wherein the indirection logic is further to receive a second sector of data associated with the host LBA, map the host LBA to a second device LBA, provide the second sector of data and the second device LBA to the NVM storage device and update a leaf node to comprise the second device LBA.

4. The apparatus of claim 1 , wherein the processor is a vector processor and the indirection logic is further to traverse a search tree to lookup a plurality of query host LBAs in parallel.

5. The apparatus of claim 1 , wherein the data portion comprises a plurality of free lists, each free list managed by a respective processor, core or thread.

6. The apparatus of claim 1 , wherein the indirection logic comprises one or more NVM primitive(s) corresponding to one or more of atomic write, atomic discard, atomic multi-write, atomic multi-discard, sparse addressing and verify.

7. A method comprising:

receiving, by indirection logic, a host logical block address (LBA) associated with a first sector of data;

mapping, by the indirection logic, the host LBA from a host address space to a first device LBA in a device address space, wherein the device address space is related to a non-volatile memory (NVM) storage device physical memory address space and comprises metadata, a transaction log and a data portion;

providing, by the indirection logic, the first sector of data and the first device LBA to the NVM storage device; and

allocating, by the indirection logic, a leaf node and an extent from a free list, the extent corresponding to the first sector of data, the data portion comprising the free list, a plurality of index nodes, a plurality of leaf nodes and a plurality of extents.

8. The method of claim 7 , further comprising:

writing, by the indirection logic, the host LBA, the first device LBA and a length corresponding to the first sector of data to the leaf node.

9. The method of claim 7 , further comprising:

receiving, by the indirection logic, a second sector of data associated with the host LBA;

mapping, by the indirection logic, the host LBA to a second device LBA;

providing, by the indirection logic, the second sector of data and the second device LBA to the NVM storage device; and

updating, by the indirection logic, a leaf node to comprise the second device LBA.

10. The method of claim 7 , further comprising traversing, by the indirection logic, a search tree to lookup a plurality of query host LBAs in parallel.

11. The method of claim 7 , wherein the data portion comprises a plurality of free lists, each free list managed by a respective processor, core or thread.

12. The method of claim 7 , wherein the indirection logic comprises one or more NVM primitive(s) corresponding to one or more of atomic write, atomic discard, atomic multi-write, atomic multi-discard, sparse addressing and verify.

13. A non-transitory computer-readable storage device having stored thereon instructions that when executed by one or more processors result in the following operations comprising:

receiving a host logical block address (LBA) associated with a first sector of data;

mapping the host LBA from a host address space to a first device LBA in a device address space, wherein the device address space is related to a non-volatile memory (NVM) storage device physical memory address space and comprises metadata, transaction log and a data portion;

providing the first sector of data and the first device LBA to the NVM storage device; and

allocating a leaf node and an extent from a free list, the extent corresponding to the first sector of data, the data portion comprising the free list, a plurality of index nodes, a plurality of leaf nodes and a plurality of extents.

14. The non-transitory computer-readable storage device of claim 13 , wherein the instructions that when executed by one or more processors results in the following additional operations comprising:

writing the host LBA, the first device LBA and a length corresponding to the first sector of data to the leaf node.

15. The non-transitory computer-readable storage device of claim 13 , wherein the instructions that when executed by one or more processors results in the following additional operations comprising:

receiving a second sector of data associated with the host LBA; mapping the host LBA to a second device LBA;

providing the second sector of data and the second device LBA to the NVM storage device; and

updating a leaf node to comprise the second device LBA.

16. The non-transitory computer-readable storage device of claim 13 , wherein the instructions that when executed by one or more processors results in the following additional operations comprising:

traversing a search tree to lookup a plurality of query host LBAs in parallel.

17. The non-transitory computer-readable storage device of claim 13 , wherein the data portion comprises a plurality of free lists, each free list managed by a respective processor, core or thread.

18. The non-transitory computer-readable storage device of claim 13 , wherein the instructions comprise one or more NVM primitive(s) corresponding to one or more of atomic write, atomic discard, atomic multi-write, atomic multi-discard, sparse addressing and verify.