Waypoint generation for adaptive flash tuning
The present invention includes embodiments of systems and methods for increasing the operational efficiency and extending the estimated operational lifetime of a flash memory storage device (and its component flash memory chips, LUNs and blocks of flash memory) by monitoring the health of the device and its components and, in response, adaptively tuning the operating parameters of flash memory chips during their operational lifetime, as well as employing other less extreme preventive measures in the interim, via an interface that avoids the need for direct access to the test modes of the flash memory chips. In an offline characterization phase, “test chips” from a batch of recently manufactured flash memory chips are used to simulate various usage scenarios and measure the performance effects of writing and attempting to recover (read) test patterns written with different sets of operating parameters over time (simulating desired retention periods).
1. An offline characterization system that generates, during an offline characterization phase prior to the operational lifetime of a flash memory chip, a plurality of alternative sets of read operating parameter values associated with a LUN in the flash memory chip, wherein the flash memory chip includes one or more LUNs, each LUN includes one or more blocks of flash memory and an associated set of one or more n-bit control registers, and each control register stores the value of an operating parameter associated with that LUN, the offline characterization system comprising:
(a) a set of write and erase operating parameter values stored in the control registers of the flash memory chip;
(b) a pattern generator that generates test pattern data to be written to and read from the one or more blocks of flash memory;
(c) a flash test controller that writes the test pattern data into the one or more blocks of flash memory in accordance with the set of write and erase operating parameter values, and reads the test pattern data following a simulated retention period, wherein the retention period is simulated by baking the flash memory chip using standard accelerated temperature-testing techniques; and
(d) a Vt window generator that, upon completion of the simulated retention period:
(i) performs a read sweep by invoking the flash test controller to perform a plurality of read operations, wherein each read operation includes an attempt to read the test pattern data from the one or more blocks of flash memory in accordance with a different set of read operating parameter values,
(ii) identifies a Vt window in which the read operations of the read sweep successfully read the test pattern data, wherein the Vt window represents a range of threshold voltage levels, and wherein each threshold voltage level corresponds to a different set of read operating parameter values, and
(iii) identifies, as an alternative set of read operating parameter values, each set of read operating parameter values corresponding to a threshold voltage level within the Vt window.
2. The offline characterization system of claim 1 , adapted to generate, for each of a plurality of health stages, a plurality of alternative sets of read operating parameter values associated with the set of write and erase operating parameter values utilized in connection with that health stage.
3. The offline characterization system of claim 1 , wherein the set of write and erase operating parameter values is generated utilizing a model that predicts the results of performing read, write and erase operations on the flash memory chip in accordance with the set of write and erase operating parameter values.
4. The offline characterization system of claim 3 , wherein
(a) the model is a non-linear function that generates a score as a function of the set of write and erase operating parameter values, and
(b) the score represents a prediction of (i) the time that would be required to perform a write operation on the flash memory chip in accordance with the set of write and erase operating parameter values, (ii) the time that would be required to perform an erase operation on the flash memory chip in accordance with the set of write and erase operating parameter values, or (iii) the success or failure of a read operation that would be performed on the flash memory chip in accordance with the set of write and erase operating parameter values.
5. The offline characterization system of claim 1 , adapted to determine the set of write and erase operating parameter values by narrowing down the number of permutations of write and erase operating parameter values, the offline characterization system further comprising:
(a) a mask generator to generate a plurality of masks, each mask corresponding to a set of write and erase operating parameter values, wherein each operating parameter value is associated either with a low mask (L) value having a range of values between 0 and ((2 n /2)−1), or a high mask (H) value having a range of values between (2 n /2) and (2 n −1); and
(b) a candidate generator for generating a candidate set of write and erase operating parameter values for each of the 2 R mask permutations, where R represents the number of control registers in each LUN of the flash memory chip, and where each operating parameter value of each candidate set is determined by generating a random number within the range of values of the low mask (L) value or high mask (H) value associated with that operating parameter value.
6. A method for generating, during an offline characterization phase prior to the operational lifetime of a flash memory chip, a plurality of alternative sets of read operating parameter values associated with a LUN in the flash memory chip, wherein the flash memory chip includes one or more LUNs, each LUN includes one or more blocks of flash memory and an associated set of one or more control registers, and each control register stores the value of an operating parameter associated with that LUN, the method comprising the following steps:
(a) storing a set of write and erase operating parameter values in the control registers of the flash memory chip;
(b) writing test pattern data into the one or more blocks of flash memory in accordance with the set of write and erase operating parameter values;
(c) simulating a period of retention by baking the flash memory chip using standard accelerated temperature-testing techniques;
(d) performing a read sweep, upon completion of the simulated retention period, by performing a plurality of read operations, wherein each read operation includes an attempt to read the test pattern data from the one or more blocks of flash memory in accordance with a different set of read operating parameter values;
(e) identifying a Vt window in which the read operations of the read sweep successfully read the test pattern data, wherein the Vt window represents a range of threshold voltage levels, and wherein each threshold voltage level corresponds to a different set of read operating parameter values; and
(f) identifying, as an alternative set of read operating parameter values, each set of read operating parameter values corresponding to a threshold voltage level within the Vt window.
7. The method of claim 6 , further comprising the step of generating, for each of a plurality of health stages, a plurality of alternative sets of read operating parameter values associated with the set of write and erase operating parameter values utilized in connection with that health stage.
8. The method of claim 6 , further comprising the step of generating the set of write and erase operating parameter values by utilizing a model that predicts the results of performing read, write and erase operations on the flash memory chip in accordance with the set of write and erase operating parameter values.
9. The method of claim 8 , wherein
(a) the model is a non-linear function that generates a score as a function of the set of write and erase operating parameter values, and
(b) the score represents a prediction of (i) the time that would be required to perform a write operation on the flash memory chip in accordance with the set of write and erase operating parameter values, (ii) the time that would be required to perform an erase operation on the flash memory chip in accordance with the set of write and erase operating parameter values, or (iii) the success or failure of a read operation that would be performed on the flash memory chip in accordance with the set of write and erase operating parameter values.
10. The method of claim 6 , further comprising the following steps to determine the set of write and erase operating parameter values by narrowing down the number of permutations of write and erase operating parameter values:
(a) generating a plurality of masks, each mask corresponding to a set of write and erase operating parameter values, wherein each operating parameter value is associated either with a low mask (L) value having a range of values between 0 and ((2 n /2)−1), or a high mask (H) value having a range of values between (2 n /2) and (2 n −1); and
(b) generating a candidate set of write and erase operating parameter values for each of the 2 R mask permutations, where R represents the number of control registers in each LUN of the flash memory chip, and where each operating parameter value of each candidate set is determined by generating a random number within the range of values of the low mask (L) value or high mask (H) value associated with that operating parameter value.