Thin film transistor substrate and manufacturing method thereof
View Patent ↗A thin film transistor array panel includes a first substrate, a gate line disposed on the first substrate and includes a lower layer including titanium, a middle layer including a transparent conductive material, and an upper layer including copper, a pixel electrode disposed on the first substrate and includes a lower layer including titanium, and an upper layer including the transparent conductive material, a gate insulating layer disposed on the gate line and the pixel electrode, a semiconductor layer disposed on the gate insulating layer, a data line and a drain electrode disposed on the semiconductor layer, a passivation layer which covers the data line and the drain electrode, and a common electrode disposed on the passivation layer.
1. A method of manufacturing a thin film transistor array panel, comprising:
sequentially depositing a lower layer including titanium, a middle layer including a transparent conductive material, and an upper layer including copper, on a substrate;
forming a gate line and a common electrode by using an etchant which etches titanium and copper;
entirely etching copper on the common electrode by using an etchant which only etches the copper on the common electrode;
forming a gate insulating layer which covers the gate line and the common electrode;
forming a semiconductor layer, a data line, and a drain electrode on the gate insulating layer;
forming a passivation layer which covers the data line and the drain electrode;
defining a contact hole exposing a part of the drain electrode, in the passivation layer; and
forming a pixel electrode connected to the drain electrode through the contact hole, on the passivation layer,
wherein the gate line includes a lower layer including titanium, a middle layer including a transparent conductive material, and an upper layer including copper, and
the common electrode consists of a lower layer and an upper layer, the lower layer including titanium and the upper layer including a transparent conductive material.
2. The method of claim 1 , wherein
a thickness of the lower layer of the gate line and the common electrode including titanium in a cross section is in a range of about 20 angstrom to about 200 angstrom.
3. The method of claim 2 , wherein
a thickness of the middle layer including the transparent conductive material in the cross section is in a range of about 400 angstrom to about 500 angstrom and
a thickness of the upper layer of the common electrode including the transparent conductive material in the cross section is in a range of about 400 angstrom to about 500 angstrom.