IP Library › Granted Patent US 9,647,645

Granted Patent B1

US 9,647,645 · App. 15/152,207 · Granted May 9, 2017

Low voltage to high voltage level translator that is independent of the high supply voltage

Inventors: Gregory L. Schaffer (Cupertino, CA); Maarten Jeroen Fonderie (Santa Clara, CA)

Assignee: XCELSEM, LLC

H03K3/356

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Quick Facts

Patent No.: US 9,647,645
App. No.: 15/152,207
Granted: May 9, 2017
Kind: B1

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Abstract

A low voltage to high voltage level translator that is independent of the high supply voltage. The translator includes first and second transistors with current terminals coupled to a first supply voltage and control terminals that are cross-coupled to one of first and second output nodes. The translator includes first and second input stages each having a first current terminal coupled to a second supply voltage, having a second current terminal coupled to one of the first and second output nodes, and having a control terminal coupled to one of first and second input nodes. The translator further includes first and second resistors, each having a first terminal coupled to the second current terminal of one of the first and second transistors and a second terminal coupled to one of the first and second output nodes. The added resistors enable wider voltage translation and avoid conventional configuration issues.

Claims (64)

1. A low voltage to high voltage level translator, comprising:

a first transistor of a first conductivity type having a first current terminal coupled to a first supply voltage, having second current terminal, and having a control terminal coupled to a first output node;

a second transistor of said first conductivity type having a first current terminal coupled to said first supply voltage, having second current terminal, and having a control terminal coupled to a second output node;

a first resistor having a first terminal coupled to said second current terminal of said first transistor of said first conductivity type, and having a second terminal coupled to said second output node;

a second resistor having a first terminal coupled to said second current terminal of said second transistor of said first conductivity type, and having a second terminal coupled to said first output node;

a first input stage of a second conductivity type having a first current terminal coupled to a second supply voltage, having a second current terminal coupled to said second output node, and having a control terminal coupled to a first input node;

a second input stage of said second conductivity type having a first current terminal coupled to said second supply voltage, having a second current terminal coupled to said first output node, and having a control terminal coupled to a second input node;

wherein said first input stage comprises a first transistor of said second conductivity type and wherein said second input stage comprises a second transistor of said second conductivity type; and

wherein said first and second transistors of said second conductivity type each have a width to length dimension ratio that depends only on a threshold voltage of said first and second transistors of said first conductivity type and a resistance of said first and second resistors.

2. The low voltage to high voltage level translator of claim 1 , wherein said first conductivity type comprises P-type and wherein said second conductivity type comprises N-type.

3. The low voltage to high voltage level translator of claim 1 , wherein said first and second transistors of said first conductivity type comprise P-channel transistors and wherein said first and second input stages of said second conductivity type comprise N-channel transistors.

4. The low voltage to high voltage level translator of claim 3 , wherein said P-channel transistors and said N-channel transistors comprise field-effect transistors.

5. The low voltage to high voltage level translator of claim 3 , wherein said P-channel and N-channel transistors comprise MOS transistors.

6. The low voltage to high voltage level translator of claim 1 , wherein said first conductivity type comprises N-type and wherein said second conductivity type comprises P-type.

7. The low voltage to high voltage level translator of claim 1 , wherein said first and second transistors of said first conductivity type comprise N-channel transistors and wherein said first and second input stages of said second conductivity type comprise P-channel transistors.

8. The low voltage to high voltage level translator of claim 7 , wherein said P-channel transistors and said N-channel transistors comprise field-effect transistors.

9. The low voltage to high voltage level translator of claim 7 , wherein said P-channel and N-channel transistors comprise MOS transistors.

10. A low voltage to high voltage level translator, comprising:

wherein said first input stage comprises a first transistor of said second conductivity type and wherein said second input stage comprises a second transistor of said second conductivity type; and

wherein said first and second transistors of said second conductivity type each have a width to length dimension ratio that does not depend upon either a width to length dimension ratio or an overdrive voltage of said first and second transistors of said first conductivity type.

11. A low voltage to high voltage level translator, comprising:

wherein said first input stage comprises a first transistor of said second conductivity type and wherein said second input stage comprises a second transistor of said second conductivity type; and

wherein said first and second transistors of said second conductivity type each have a width to length dimension ratio that is independent of a magnitude of said first supply voltage relative to said second supply voltage.

12. A low voltage to high voltage level translator, comprising:

wherein said first input stage comprises:

a first transistor of said second conductivity type having a first current terminal coupled to said second supply voltage, having a second current terminal, and having a control terminal coupled to said first input node; and

a second transistor of said second conductivity type having a first current terminal coupled to said second current terminal of said first transistor of said second conductivity type, having a second current terminal coupled to said second output node, and having a control terminal coupled to a bias voltage; and

wherein said second input stage comprises:

a third transistor of said second conductivity type having a first current terminal coupled to said second supply voltage, having a second current terminal, and having a control terminal coupled to said second input node; and

a fourth transistor of said second conductivity type having a first current terminal coupled to said second current terminal of said third transistor of said second conductivity type, having a second current terminal coupled to said first output node, and having a control terminal coupled to said bias voltage.

13. The low voltage to high voltage level translator of claim 12 , wherein said first and third transistors of said second conductivity type each have a width to length dimension ratio that depends only on a threshold voltage of said first and second transistors of said first conductivity type and a resistance of said first and second resistors.

14. The low voltage to high voltage level translator of claim 12 , wherein said first and third transistors of said second conductivity type each have a width to length dimension ratio that does not depend upon either a width to length dimension ratio or an overdrive voltage of said first and second transistors of said first conductivity type.

15. The low voltage to high voltage level translator of claim 12 , wherein said first and third transistors of said second conductivity type each have a width to length dimension ratio that is independent of a magnitude of said first supply voltage relative to said second supply voltage.

16. The low voltage to high voltage level translator of claim 12 , wherein:

said first and second input nodes each receive an input voltage having a voltage range within a first magnitude, and wherein said first and second output nodes each provide an output voltage having a voltage range within a second magnitude that is greater than said first magnitude; and

wherein said first and third transistors of said second conductivity type each have a width to length dimension ratio that is independent of said second magnitude.

17. The low voltage to high voltage level translator of claim 12 , wherein said first and second transistors of said first conductivity type comprise P-channel transistors, and wherein said first, second, third and fourth transistors of said second conductivity type comprise N-channel transistors.

18. The low voltage to high voltage level translator of claim 12 , wherein said first and second transistors of said first conductivity type comprise N-channel transistors, and wherein said wherein said first, second, third and fourth transistors of said second conductivity type comprise P-channel transistors.

19. A low voltage to high voltage level translator, comprising:

wherein said first and second input stages of said second conductivity type each comprise a cascode stage of a plurality of transistors of said second conductivity type.

Assignments (2)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2022

From: XCELSEM, LLC

To: FONDERIE, MAARTEN JEROEN

Reel/Frame 060325/0482 →

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2016

From: SCHAFFER, GREGORY L.; FONDERIE, MAARTEN JEROEN

To: XCELSEM, LLC

Reel/Frame 038551/0953 →