Display substrate and method of fabricating the same

1. A display substrate, comprising:

a common electrode formed on a substrate;

an insulating layer formed on the common electrode;

a gate pattern formed on the insulating layer comprising a gate electrode and a common electrode contact part spaced apart from the gate electrode;

a gate insulating layer formed on the gate pattern;

a semiconductor layer disposed on the gate insulating layer;

a source electrode and a drain electrode formed on the semiconductor layer;

a passivation layer formed on the source electrode and the drain electrode;

a pixel electrode formed on the passivation layer; and

a common electrode contact connection part spaced apart from the pixel electrode

wherein the common electrode-contact connection part directly contacts a side surface of the common electrode contact part.

2. The display substrate of claim 1 , wherein the common electrode is deposited on an entire surface of the substrate.

3. The display substrate of claim 1 , wherein the common electrode and the pixel electrode each comprise a transparent conductive oxide-based material (TCO-based material).

4. The display substrate of claim 1 , wherein the insulating layer and the gate insulating layer comprise a silicon-based material.

5. The display substrate of claim 1 , wherein the gate electrode, the source electrode, and the drain electrode each comprise at least one of copper, aluminum, molybdenum, tungsten, titanium, and chrome.

6. A method of fabricating a display substrate, comprising:

depositing a common electrode on a surface of a substrate;

depositing an insulating layer on the common electrode;

depositing a first metal layer on the insulating layer;

patterning the first metal layer on the insulating layer to form a gate electrode and a common electrode contact part;

depositing a gate insulating layer on the patterned first metal layer;

depositing a semiconductor material on the gate insulating layer;

depositing a second metal layer on the semiconductor layer;

patterning the second metal layer and the semiconductor layer to form a source electrode and a drain electrode and the semiconductor pattern;

depositing a passivation layer on the patterned second metal layer;

patterning a passivation layer to form a first contact hole over the drain electrode and a second contact hole over a portion of the common electrode contact part and a portion of the common electrode adjacent to the common electrode contact part;

depositing a transparent conductive oxide-based material (TCO-based material) on the passivation layer; and

patterning the TCO-based material to form a pixel electrode and a common electrode-contact connection part that directly contacts a side surface of the common electrode contact part.

7. The method of claim 6 , wherein patterning the first metal layer on the insulating layer to form the gate electrode and the common electrode contact part, further comprises:

wet etching the first metal layer, and

dry etching the insulating layer.

8. The method of claim 6 , wherein a half-tone (HT) mask is used to pattern the second metal layer and the semiconductor layer to form a source electrode and a drain electrode and the semiconductor pattern.

9. The method of claim 6 , wherein the second contact hole is formed over a portion of the common electrode that is immediately adjacent to the common electrode contact part.

10. The method of claim 7 , wherein the common electrode-contact connection part directly contacts the common electrode.