Method and apparatus for determining thread execution parallelism
An apparatus and method for determining thread execution parallelism. For example, a processor in accordance with one embodiment comprises: a plurality of cores to execute a plurality of threads; a plurality of counters to collect data related to the execution of the plurality of threads on the plurality of cores; a dependency analysis module to analyze the data related to the execution of the threads and responsively determine a level of inter-thread dependency; and a control module to responsively adjust operation of the plurality of cores based on the determined level of inter-thread dependency.
1. A processor comprising:
a plurality of cores to execute a plurality of threads;
an integrated graphics unit;
a plurality of counters to collect data related to the execution of the plurality of threads on the plurality of cores, wherein the plurality of counters comprises a first counter to express an average number of physical active cores, a second counter to express an average time that any physical core was active, a third counter to express an average time that the integrated graphics unit was active, and a fourth counter to express an average time that any one of the physical cores was active in parallel with the integrated graphics unit;
dependency analysis logic circuit to analyze the data related to the execution of the threads and responsively determine a level of inter-thread dependency; and
control logic circuit to responsively adjust operation of the plurality of cores based on the determined level of inter-thread dependency.
2. The processor as in claim 1 wherein the control logic circuit is to dynamically allocate a particular number of active cores to minimize energy consumed when executing the threads.
3. The processor as in claim 1 wherein the control logic circuit is to dynamically allocate a particular number of active cores to maximize performance when executing the threads.
4. The processor as in claim 1 wherein for relatively higher levels of inter-thread dependency, the control logic circuit is to increase execution frequency on each core to speed up execution of the threads.
5. The processor as in claim 4 wherein for relatively lower levels of inter-thread dependency, the control logic circuit is to reduce the execution frequency on each core and/or inserting forced idle periods on the cores.
6. The processor as in claim 1 wherein the dependency analysis logic circuit determines an average number of active cores across active and idle phases by dividing a change in value of the first counter by a number of cycles executed in a measured time window.
7. The processor as in claim 1 wherein the dependency analysis logic circuit determines an average number of active cores when the processor is active by dividing a change in value of the first counter by a change in value of the second counter.
8. A method comprising:
executing a plurality of threads on a plurality of cores;
collecting data related to the execution of the plurality of threads on the plurality of cores using a plurality of counters, wherein the plurality of counters comprises a first counter to express an average number of physical active cores, a second counter to express an average time that any physical core was active, a third counter to express an average time that an integrated graphics unit was active, and a fourth counter to express an average time that any one of the physical cores was active in parallel with the integrated graphics unit;
analyzing the data related to the execution of the threads and responsively determining a level of inter-thread dependency; and
responsively adjusting operation of the plurality of cores based on the determined level of inter-thread dependency.
9. The method as in claim 8 wherein responsively adjusting operation of the plurality of cores comprises dynamically allocating a particular number of active cores to minimize energy consumed when executing the threads.
10. The method as in claim 8 wherein responsively adjusting operation of the plurality of cores comprises dynamically allocating a particular number of active cores to maximize performance when executing the threads.
11. The method as in claim 8 wherein for relatively higher levels of inter-thread dependency, execution frequency is adjusted on each core to speed up execution of the threads.
12. The method as in claim 11 wherein for relatively lower levels of inter-thread dependency, the execution frequency on each core is reduced and/or forced idle periods inserted on the cores.
13. The method as in claim 8 wherein analyzing the data related to the execution of the threads and responsively determining a level of inter-thread dependency comprises determining an average number of active cores across active and idle phases by dividing a change in value of the first counter by a number of cycles executed in a measured time window.
14. The method as in claim 8 wherein analyzing the data related to the execution of the threads and responsively determining a level of inter-thread dependency comprises determining an average number of active cores when in an active phase by dividing a change in value of the first counter by a change in value of the second counter.
15. A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:
executing a plurality of threads on a plurality of cores;
reading data from a plurality of counters, the data related to the execution of the plurality of threads on the plurality of cores, wherein the plurality of counters comprises a first counter to express an average number of physical active cores, a second counter to express an average time that any physical core was active, a third counter to express an average time that an integrated graphics unit was active, and a fourth counter to express an average time that any one of the physical cores was active in parallel with the integrated graphics unit;
analyzing the data related to the execution of the threads and responsively determining a level of inter-thread dependency; and
responsively adjusting operation of the plurality of cores based on the determined level of inter-thread dependency.
16. The machine-readable medium as in claim 15 wherein responsively adjusting operation of the plurality of cores comprises dynamically allocating a particular number of active cores to minimize energy consumed when executing the threads.
17. The machine-readable medium as in claim 15 wherein responsively adjusting operation of the plurality of cores comprises dynamically allocating a particular number of active cores to maximize performance when executing the threads.
18. The machine-readable medium as in claim 15 wherein for relatively higher levels of inter-thread dependency, execution frequency is adjusted on each core to speed up execution of the threads.
19. The machine-readable medium as in claim 18 wherein for relatively lower levels of inter-thread dependency, the execution frequency on each core is reduced and/or forced idle periods inserted on the cores.
20. The machine-readable medium as in claim 15 wherein analyzing the data related to the execution of the threads and responsively determining a level of inter-thread dependency comprises determining an average number of active cores across active and idle phases by dividing a change in value of the first counter by a number of cycles executed in a measured time window.
21. The machine-readable medium as in claim 15 wherein analyzing the data related to the execution of the threads and responsively determining a level of inter-thread dependency comprises determining an average number of active cores when in an active phase by dividing a change in value of the first counter by a change in value of the second counter.