IP Library Granted Patent US 9,685,321
Granted Patent B2
US 9,685,321 · App. 15/064,735 · Granted Jun 20, 2017

Semiconductor memory device and method for manufacturing the same

Inventors: Masaya Terai (Kawasaki, JP); Shigeki Hattori (Kawasaki, JP); Hideyuki Nishizawa (Toshima, JP); Koji Asakawa (Kawasaki, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L21/02282G11C11/5664H01L21/02118H01L21/28282H01L51/0591H01L27/11582H01L51/0077
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,685,321
App. No.
15/064,735
Granted
Jun 20, 2017
Kind
B2
Abstract

A semiconductor memory device in an embodiment includes a semiconductor layer, a control gate electrode, an organic molecular layer provided between the semiconductor layer and the control gate electrode, and a first insulating layer provided between the organic molecular layer and the semiconductor layer, the first insulating layer having a first layer containing alkyl chains and a second layer containing siloxane, the second layer being provided between the first layer and the organic molecular layer.

Claims (9)

1. A semiconductor memory device comprising: a semiconductor layer; a control gate electrode; an organic molecular layer provided between the semiconductor layer and the control gate electrode; and a first insulating layer provided between the organic molecular layer and the semiconductor layer, the first insulating layer having a first layer containing alkyl chains and a second layer containing siloxane, the second layer being provided between the first layer and the organic molecular layer, wherein the first insulating layer contains a structure formed by chemical bonding of a first precursor described by molecular formula (1) and a second precursor described by molecular formula (2):

wherein X, Y are independently selected from among silyl ether, phosphoryl ether, alkoxy, carbonyl, and ether, n is an integer greater than 0, R1 to R4 are independently selected from hydrogen, oxygen, silicon, hydrocarbon, halogen, halogenated silane, alkoxy silane, and silyl ether, and m is an integer greater than 0.

2. The device according to claim 1 , wherein carbon number of each of the alkyl chains is between 4 and 30 inclusive.

3. The device according to claim 1 , wherein the first layer is a monomolecular film.

4. The device according to claim 1 , further comprising an inorganic second insulating layer provided between the first insulating layer and the semiconductor layer.

5. The device according to claim 1 , further comprising a third insulating layer between the organic molecular layer and the control gate electrode.

6. The device according to claim 1 , wherein the first layer is chemically bonded to the semiconductor layer.

7. The device according to claim 4 , wherein the first layer is chemically bonded to the second insulating layer.

8. The device according to claim 1 , wherein the organic molecular layer has oxidation-reduction molecules.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043129/0295 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2016
From: TERAI, MASAYA; HATTORI, SHIGEKI; NISHIZAWA, HIDEYUKI; ASAKAWA, KOJI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 039038/0377 →
Priority Claims (1)
JP 2015-060238 · Mar 24, 2015 · national
Continuity (1)
Related Publication 20160284868A1 · Sep 29, 2016