Power-and-ground (PG) network characterization and distributed PG network creation for hierarchical circuit designs

1. In an electronic design automation (EDA) software tool in a computer, a method for creating a power-and-ground (PG) network for a chip layout, wherein the chip layout includes a top-level portion and a set of blocks, wherein the PG network for the chip layout is specified by a set of chip-level PG constraints that is defined by a user using a PG constraint definition language, the method comprising:

the EDA software tool in the computer determining a set of top-level PG constraints for creating a top-level PG network for the top-level portion of the chip layout based on the set of chip-level PG constraints, wherein the set of top-level PG constraints is defined using the PG constraint definition language;

for each block in the set of blocks, the EDA software tool in the computer determining a set of block-level PG constraints based on the set of chip-level PG constraints, wherein the set of block-level PG constraints is defined using the PG constraint definition language;

the EDA software tool in the computer creating a PG network in the top-level portion based on the set of top-level PG constraints;

for each block in the set of blocks, the EDA software tool in the computer creating a PG network in the block based on the set of block-level PG constraints associated with the block; and

wherein creating the PG network in the top-level portion and creating the PG network in each block in the set of blocks comprise providing the set of top-level PG constraints and the set of block-level PG constraints associated with each block in the set of blocks to one or more instances of a PG compiler that execute on one or more processors in the computer.

2. The method of claim 1 , wherein the PG network in the top-level portion and PG networks in the set of blocks are created concurrently by multiple instances of PG compilers.

3. The method of claim 1 , wherein the set of chip-level PG constraints comprises a set of PG network patterns defined using the PG constraint definition language, a set of instantiation areas defined using the PG constraint definition language, a set of blockage areas defined using the PG constraint definition language, and a set of via creation rules defined using the PG constraint definition language.

4. The method of claim 3 , wherein determining the set of top-level PG constraints comprises adding a blockage area constraint corresponding to each block in the set of blocks to the set of chip-level PG constraints, wherein each blockage area constraint that is added to the set of top-level PG constraints is defined using the PG constraint definition language.

5. The method of claim 4 , wherein determining the set of block-level PG constraints for each block in the set of blocks comprises:

computing an offset associated with the set of PG network patterns based on a location of the block in the chip layout;

removing instantiation areas from the set of instantiation areas that do not intersect with the block;

removing blockage areas from the set of blockage areas that do not intersect with the block;

redefining each remaining instantiation area in the set of instantiation areas to match an intersection area between the instantiation area and the block; and

redefining each remaining blockage area in the set of blockage areas to match an intersection area between the blockage area and the block.

6. A non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method for creating a power-and-ground (PG) network for a chip layout, wherein the chip layout includes a top-level portion and a set of blocks, wherein the PG network for the chip layout is specified by a set of chip-level PG constraints that is defined by a user using a PG constraint definition language, the method comprising:

determining a set of top-level PG constraints for creating a top-level PG network for the top-level portion of the chip layout based on the set of chip-level PG constraints, wherein the set of top-level PG constraints is defined using the PG constraint definition language;

for each block in the set of blocks, determining a set of block-level PG constraints based on the set of chip-level PG constraints, wherein the set of block-level PG constraints is defined using the PG constraint definition language;

creating a PG network in the top-level portion based on the set of top-level PG constraints;

for each block in the set of blocks, creating a PG network in the block based on the set of block-level PG constraints associated with the block; and

wherein creating the PG network in the top-level portion and creating the PG network in each block in the set of blocks comprise providing the set of top-level PG constraints and the set of block-level PG constraints associated with each block in the set of blocks to one or more instances of a PG compiler that execute on one or more processors in the computer.

7. The non-transitory computer-readable storage medium of claim 6 , wherein the PG network in the top-level portion and PG networks in the set of blocks are created concurrently by multiple instances of PG compilers.

8. The non-transitory computer-readable storage medium of claim 6 , wherein the set of chip-level PG constraints comprises a set of PG network patterns defined using the PG constraint definition language, a set of instantiation areas defined using the PG constraint definition language, a set of blockage areas defined using the PG constraint definition language, and a set of via creation rules defined using the PG constraint definition language.

9. The non-transitory computer-readable storage medium of claim 8 , wherein determining the set of top-level PG constraints comprises adding a blockage area constraint corresponding to each block in the set of blocks to the set of chip-level PG constraints, wherein each blockage area constraint that is added to the set of top-level PG constraints is defined using the PG constraint definition language.

10. The non-transitory computer-readable storage medium of claim 9 , wherein determining the set of block-level PG constraints for each block in the set of blocks comprises:

computing an offset associated with the set of PG network patterns based on a location of the block in the chip layout;

removing instantiation areas from the set of instantiation areas that do not intersect with the block;

removing blockage areas from the set of blockage areas that do not intersect with the block;

redefining each remaining instantiation area in the set of instantiation areas to match an intersection area between the instantiation area and the block; and

redefining each remaining blockage area in the set of blockage areas to match an intersection area between the blockage area and the block.

11. An apparatus, comprising:

one or more processors; and

a non-transitory computer-readable storage medium storing instructions that, when executed by the one or more processors, cause the apparatus to perform a method for creating a power-and-ground (PG) network for a chip layout, wherein the chip layout includes a top-level portion and a set of blocks, wherein the PG network for the chip layout is specified by a set of chip-level PG constraints that is defined by a user using a PG constraint definition language, the method comprising:

determining a set of top-level PG constraints for creating a top-level PG network for the top-level portion of the chip layout based on the set of chip-level PG constraints, wherein the set of top-level PG constraints is defined using the PG constraint definition language;

for each block in the set of blocks, determining a set of block-level PG constraints based on the set of chip-level PG constraints, wherein the set of block-level PG constraints is defined using the PG constraint definition language;

creating a PG network in the top-level portion based on the set of top-level PG constraints;

for each block in the set of blocks, creating a PG network in the block based on the set of block-level PG constraints associated with the block; and

wherein creating the PG network in the top-level portion and creating the PG network in each block in the set of blocks comprise providing the set of top-level PG constraints and the set of block-level PG constraints associated with each block in the set of blocks to one or more instances of a PG compiler that execute on the one or more processors.

12. The apparatus of claim 11 , wherein the PG network in the top-level portion and PG networks in the set of blocks are created concurrently by multiple instances of PG compilers.

13. The apparatus of claim 11 , wherein the set of chip-level PG constraints comprises a set of PG network patterns defined using the PG constraint definition language, a set of instantiation areas defined using the PG constraint definition language, a set of blockage areas defined using the PG constraint definition language, and a set of via creation rules defined using the PG constraint definition language.

14. The apparatus of claim 13 , wherein determining the set of top-level PG constraints comprises adding a blockage area constraint corresponding to each block in the set of blocks to the set of chip-level PG constraints, wherein each blockage area constraint that is added to the set of top-level PG constraints is defined using the PG constraint definition language.

15. The apparatus of claim 14 , wherein determining the set of block-level PG constraints for each block in the set of blocks comprises:

computing an offset associated with the set of PG network patterns based on a location of the block in the chip layout;

removing instantiation areas from the set of instantiation areas that do not intersect with the block;

removing blockage areas from the set of blockage areas that do not intersect with the block;

redefining each remaining instantiation area in the set of instantiation areas to match an intersection area between the instantiation area and the block; and

redefining each remaining blockage area in the set of blockage areas to match an intersection area between the blockage area and the block.