IP Library Granted Patent US 9,748,937
Granted Patent B1
US 9,748,937 · App. 15/155,687 · Granted Aug 29, 2017

Superconducting digital phase rotator

Inventor: Amol Ashok Inamdar (Elmsford, NY)
Assignee: Hypres, Inc.
H03K5/131H03K3/38H03L7/16H03K2005/00286
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Quick Facts
Patent No.
US 9,748,937
App. No.
15/155,687
Granted
Aug 29, 2017
Kind
B1
Abstract

An important component in digital circuits is a phase rotator, which permits precise time-shifting (or equivalently, phase rotation) of a clock signal within a clock period. A digital phase rotator can access multiple discrete values of phase under digital control. Such a device can have application in digital clock synchronization circuits, and can also be used for a digital phase modulator that encodes a digital signal. A digital phase rotator has been implemented in superconducting integrated circuit technology, using rapid single-flux-quantum logic (RSFQ). This circuit can exhibit positive or negative phase shifts of a multi-phase clock. Arbitrary precision can be obtained by cascading a plurality of phase rotator stages. Such a circuit forms a phase-modulator that is the core of a direct digital synthesizer that can operate at multi-gigahertz radio frequencies.

Claims (34)

1. A cascaded direct digital synthesizer, configured to generate a radio frequency signal, comprising:

a plurality of digital control input ports, each digital control input port being configured to receive a respective digital signal comprising pulses, comprising a plurality of advance phase control input ports, each configured to receive an advance phase control signal and a plurality of retard phase control input ports each configured to receive a retard phase control signal;

a first synchronizer, configured to synchronize a first portion of the pulses received at the plurality of digital control input ports with respect to an input digital signal comprising a sequence of pulses of the digital input signal having a rate in excess of 1 gigasamples per second, to produce a first set of synchronized pulses;

a first digital phase modulator, configured to receive the respective first set of synchronized pulses and the sequence of pulses of the digital input signal, and to produce selectively in dependence thereon a first digitally modulated pulse train, comprising logic configured to insert a pulse into the pulse stream in response to the advance phase control signal, and to suppress a pulse from the pulse stream selectively in response to the retard phase control signal;

a second synchronizer, configured to synchronize a second portion of the pulses received at the plurality of digital control input ports with respect to the input digital signal comprising the sequence of pulses of the digital input signal having the rate in excess of 1 gigasamples per second, to produce a second set of synchronized pulses; and

a second digital phase modulator, configured to receive the respective second set of synchronized pulses and the first digitally modulated pulse train, and to produce selectively in dependence thereon a second digitally modulated pulse train, comprising logic configured to insert a pulse into the pulse stream in response to the advance phase control signal, and to suppress a pulse from the pulse stream selectively in response to the retard phase control signal.

2. The cascaded direct digital synthesizer according to claim 1 , further comprising a filter and an output amplifier configured to convert the digitally modulated pulse train to a radio frequency analog signal.

3. The cascaded direct digital synthesizer according to claim 1 , wherein each of the first digital phase modulator and the second digital phase modulator comprises at least one Josephson junction.

4. The cascaded direct digital synthesizer according to claim 1 , wherein each of the first synchronizer and the second synchronizer comprises at least one Josephson junction.

5. The cascaded digital synthesizer according to claim 1 , wherein the input signal comprises a clock signal having the clock rate in excess of 1 gigahertz, further comprising a clock input configured to receive the clock signal.

6. The cascaded direct digital synthesizer according to claim 1 , wherein each digital control input port is configured to receive a digital pulse train at a rate in excess of 1 gigasamples per second.

7. The cascaded direct digital synthesizer according to claim 1 , wherein the digitally modulated pulse train comprises a sequence of single flux quantum (SFQ) pulses.

8. The cascaded direct synthesizer according to claim 1 , wherein the first digital phase modulator comprises a decimator configured to generate a decimated pulse stream.

9. The cascaded direct digital synthesizer according to claim 1 , wherein the plurality of digital control input ports comprise an advance phase control input port configured to receive an advance phase control signal and a retard phase control input port configured to receive a retard phase control signal.

10. The cascaded direct digital synthesizer according to claim 9 , wherein each of the first digital phase modulator and the second digital phase modulator comprises: a decimator configured to generate a decimated pulse stream from the sequence of pulses: and logic configured to at least one of: insert a pulse into the decimated pulse stream, and suppress a pulse from the decimated pulse stream.

11. The cascaded direct digital synthesizer according to claim 1 , comprising at least two Josephson junctions on an integrated circuit.

12. The cascaded direct digital synthesizer according to claim 1 , wherein at least one of the plurality of digital control input ports is configured to receive a multi-bit digital pulse signal.

13. A cascaded direct digital synthesizer, configured to generate a radio frequency analog signal, comprising a plurality of cascaded stages, each stage comprising:

a plurality of respective digital control input ports, each digital control input port being configured to receive a respective signal for controlling a modulation by the respective stage;

a synchronizer, configured to synchronize the plurality of digital control input ports with respect to an input signal to the respective stage; and

a digital phase modulator, configured to selectively produce a modulated pulse train, selectively in dependence on the respective signals for controlling a modulation by the respective stage, and the input signal to the respective stage being an input signal from an input signal port for a first respective stage, and the modulated pulse train from a preceding respective stage for subsequent stages.

14. The cascaded direct digital synthesizer according to claim 13 , wherein each stage comprises at least one Josephson junction.

15. The cascaded direct digital synthesizer according to claim 13 , wherein the modulated pulse train comprises a sequence of single flux quantum pulses.

16. The cascaded direct digital synthesizer according to claim 13 , wherein the input signal port is configured to receive a digital pulse train at a rate in excess of 1 gigasample/sec, further comprising an output amplifier configured to convert the modulated pulse train of a final stage to a radio frequency analog signal.

17. The cascaded direct digital synthesizer according to claim 13 , wherein the plurality of respective digital control input ports comprise an advance phase control input port configured to receive an advance phase control signal and a retard phase control input port configured to receive a retard phase control signal, further comprising a decimator configured to generate a decimated pulse stream.

18. A method for directly synthesizing a digital radio frequency signal, comprising:

providing a cascaded direct digital synthesizer, configured to generate a radio frequency analog signal, comprising a plurality of cascaded stages, each stage comprising:

a plurality of respective digital control input ports, each digital control input port being configured to receive a respective signal for controlling a modulation by the respective stage;

a synchronizer, configured to synchronize the plurality of digital control input ports with respect to an input signal to the respective stage; and

a digital phase modulator, configured to selectively produce a modulated pulse train, selectively in dependence on the respective signals for controlling a modulation by the respective stage, and the input signal to the respective stage being an input signal from an input signal port for a first respective stage, and the modulated pulse train from a preceding respective stage for subsequent stages;

receiving a respective control signal pulse stream for controlling a modulation of each respective stage, from each of a plurality of digital control input ports, each respective control signal pulse stream having a pulse stream control clock rate of at least 1 gigahertz;

digitally synchronizing the plurality of control signal pulse streams with respect to an input signal comprising a sequence of pulses having an input signal clock rate in excess of 1 gigahertz, to produce a plurality of synchronized control signal pulse streams; and

digitally modulating a phase of the sequence of pulses of a respective input signal to each stage, to produce selectively in dependence thereon a respective digitally modulated pulse train, selectively dependent on the respective plurality of synchronized control signal pulse streams, wherein a respective digitally modulated pulse train of a first stage is received as the respective input signal of a subsequent stage.

19. The method according to claim 18 , further comprising digitally decimating the sequence of pulses with a decimator, wherein said digitally modulating the phase comprises addition of at least one pulse to, or suppression of at least one pulse from, the input signal.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Aug 6, 2024
From: AVIDBANK
To: HYPRES, INC.
Reel/Frame 068348/0909 →
SECURITY INTEREST Recorded Jun 17, 2021
From: HYPRES, INC.
To: AVIDBANK
Reel/Frame 056617/0116 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2016
From: INAMDAR, AMOL
To: HYPRES, INC.
Reel/Frame 039541/0513 →
Continuity (5)
Continuation 14743409 · Jun 18, 2015
Continuation 13073942 · Mar 28, 2011
Continuation 11625013 · Jan 19, 2007
Continuation In Part 11617806 · Dec 29, 2006
Provisional Application 60840379 · Aug 25, 2006