IP Library Granted Patent US 9,753,799
Granted Patent B2
US 9,753,799 · App. 14/891,339 · Granted Sep 5, 2017

Conditional pattern detector for detecting hangs

Inventors: Rodney E. Hooker (Austin, TX); Douglas R. Reed (Austin, TX)
Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
G06F11/079G06F9/46G06F11/073G06F11/0751G06F11/0787G06F11/1451G06F12/0855G06F2201/805G06F2201/84G06F2212/1041G06F2212/608
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Quick Facts
Patent No.
US 9,753,799
App. No.
14/891,339
Granted
Sep 5, 2017
Kind
B2
Abstract

A microprocessor comprises a cache including a tag array; a tag pipeline that arbitrates access to the tag array; and a pattern detector. The pattern detector comprises snapshot capture logic that captures snapshots of tagpipe arbs—including information about whether the tagpipe arb is a load, snoop, store or other arb type and whether the tagpipe arb completed or replayed—and a plurality of configurable register modules operable to store user-configured snapshot patterns. Configuration logic enables a user to specify, for each configurable register module, properties of tagpipe arbs for the pattern detector to detect as well as dependencies between the configurable register modules. A register module becomes triggered if a tagpipe arb or pattern of tagpipe arbs meets the user-specified properties for the register module and if any other register module on which the register module depends is also in a triggered state.

Claims (45)

1. A microprocessor comprising:

a cache including a tag array;

a tag pipeline that arbitrates access to the tag array; and

a pattern detector, the pattern detector comprising:

snapshot capture logic that captures snapshots of tagpipe arbs, wherein tagpipe arbs are transactions to access the tag array;

a plurality of configurable register modules operable to store user-configured snapshot patterns; and

configuration logic that enables a user to specify, for each configurable register module, properties of tagpipe arbs for the pattern detector to detect;

the configurable logic further enabling the user to specify one or more dependencies between the configurable register modules;

wherein the pattern detector is configured to detect patterns of arbs that match the user-specified properties and dependencies set forth in the configurable register modules.

2. The microprocessor of claim 1 , wherein the snapshot capture logic obtains information about whether the tagpipe arb is a load, snoop, store or other arb type.

3. The microprocessor of claim 1 , wherein the snapshot capture logic obtains information about whether the tagpipe arb completed or replayed.

4. The microprocessor of claim 1 , wherein each register module is operable to be triggered and to provide a signal indicative of its triggered state to each of the other register modules.

5. The microprocessor of claim 1 , wherein a first register module is configured to be in a triggered state upon satisfaction of one or more predetermined conditions.

6. The microprocessor of claim 5 , wherein one of the one or more predetermined conditions is a detection of a tagpipe arb or pattern of tagpipe arbs that meets the user-specified properties for the first register module.

7. The microprocessor of claim 6 , wherein if the first register module is specified as being dependent on a second register module, then another predetermined condition is the second register module being in a triggered state.

8. The microprocessor of claim 7 , wherein:

the configuration logic enables a user to optionally specify and configure, for the second register module, a timeout period, wherein the timeout period starts when the second register module indicates that it is in a triggered state; and

after expiration of the timeout period, the pattern detector is operable to disable the first register module from entering into a triggered state.

9. The microprocessor of claim 1 , wherein the snapshot capture logic is coupled to a stage of the tag pipeline by which point it has been determined whether an arb is going to replay, complete, and/or require other queue pushes.

10. The microprocessor of claim 1 , wherein the pattern detector is configured to trigger an information storage routine or recovery routine if a register module upon which no other register module is conditioned enters into a triggered state.

11. A method of detecting patterns of arbs in a microprocessor having a cache including a tag array, a tag pipeline that arbitrates access to the tag array, and a pattern detector, the method comprising:

capturing snapshots of tagpipe arbs, wherein tagpipe arbs are transactions to access the tag array;

storing user-configured snapshot patterns in a plurality of configurable register modules;

specifying, for each configurable register module, properties of tagpipe arbs for the pattern detector to detect; and

specifying one or more dependencies between the configurable register modules.

12. The method of claim 11 , wherein the snapshots comprise information about whether the tagpipe arb is a load, snoop, store or other arb type.

13. The method of claim 11 , wherein the snapshot comprises information about whether the tagpipe arb completed or replayed.

14. The method of claim 11 , further comprising providing a signal indicative of a register module's triggered state to each other register module that depends from it.

15. The method of claim 11 , further comprising configuring a first one of the register modules to be in a triggered state upon satisfaction of one or more predetermined conditions.

16. The method of claim 15 , wherein one of the one or more predetermined conditions is a tagpipe arb or pattern of tagpipe arbs meeting the specified properties for the first register module.

17. The method of claim 16 , further comprising specifying the first register module as being dependent on a second register module, wherein another predetermined condition is the second register module being in a triggered state.

18. The method of claim 17 , further comprising:

configuring a timeout period for the second register module, wherein the timeout period starts when the second register module indicates that it is in a triggered state; and

after expiration of the timeout period, disabling the first register module from entering into a triggered state.

19. The method of claim 11 , further comprising triggering an information storage routine or recovery routine if a register module upon which no other register module is conditioned enters into a triggered state.

20. A computer program product encoded in at least one non-transitory computer readable medium for use with a computing device, the computer program product comprising:

computer readable program code embodied in said medium, for specifying a microprocessor that has:

a cache including a tag array;

a tag pipeline that arbitrates access to the tag array; and

a pattern detector, the pattern detector comprising:

snapshot capture logic that captures snapshots of tagpipe arbs, wherein tagpipe arbs are transactions to access the tag array;

a plurality of configurable register modules operable to store user-configured snapshot patterns; and

configuration logic that enables a user to specify, for each configurable register module, properties of tagpipe arbs for the pattern detector to detect;

the configurable logic further enabling the user to specify one or more dependencies between the configurable register modules;

wherein the pattern detector is configured to detect patterns of arbs that match the user-specified properties and dependencies set forth in the configurable register modules.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2015
From: HOOKER, RODNEY E.; REED, DOUGLAS R.
To: VIA ALLIANCE SEMICONDUCTOR CO., LTD
Reel/Frame 037041/0710 →
Continuity (1)
Related Publication 20160350167A1 · Dec 1, 2016