IP Library Granted Patent US 9,754,888
Granted Patent B2
US 9,754,888 · App. 15/133,523 · Granted Sep 5, 2017

Semiconductor memory device and method for manufacturing the same

Inventors: Kazuhito Furumoto (Mie, JP); Toshiyuki Sasaki (Mie, JP)
Assignee: Toshiba Memory Corporation
H01L23/53266H01L21/76816H01L21/76843H01L21/76897H01L23/5226H01L23/5283H01L27/1157H01L27/11582
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Quick Facts
Patent No.
US 9,754,888
App. No.
15/133,523
Granted
Sep 5, 2017
Kind
B2
Abstract

A semiconductor memory device according to one embodiment includes a plurality of lower electrode films stacked separated from each other, an upper electrode film provided above the plurality of lower electrode films, a semiconductor pillar extending in an arrangement direction of the plurality of lower electrode films and the upper electrode film, a memory film provided between the semiconductor pillar and one of the plurality of lower electrode films and between the semiconductor pillar and the upper electrode film, and a metal-containing layer provided at least one of on a lower surface and an upper surface of the one of the plurality of lower electrode films and between the one of the plurality of lower electrode films and the memory film, the metal-containing layer having a composition different from a composition of the plurality of lower electrode films. The upper electrode film is in contact with the memory film.

Claims (52)

1. A semiconductor memory device comprising:

a plurality of lower electrode films stacked separated from each other;

an upper electrode film provided above the plurality of lower electrode films;

a semiconductor pillar extending in an arrangement direction of the plurality of lower electrode films and the upper electrode film;

a memory film provided between the semiconductor pillar and one of the plurality of lower electrode films and between the semiconductor pillar and the upper electrode film; and

a metal-containing layer provided at at least one of on a lower surface and an upper surface of the one of the plurality of lower electrode films and between the one of the plurality of lower electrode films and the memory film, the metal-containing layer having a composition different from a composition of the plurality of lower electrode films,

the upper electrode film being in contact with the memory film, and the one of the plurality of lower electrode films not being in contact with the memory film.

2. The device according to claim 1 , wherein

the upper electrode film is thicker than the one of the plurality of lower electrode films in the arrangement direction.

3. The device according to claim 1 , wherein

a plurality of the upper electrode films are provided, and the plurality of upper electrode films are arranged separated from each other along the arrangement direction.

4. The device according to claim 1 , wherein

the metal-containing layer contains one or more kinds of metals selected from the group consisting of titanium, tantalum, and tungsten, and the metal-containing layer contains nitrogen.

5. The device according to claim 1 , wherein

the metal-containing layer is not provided on a lower surface and an upper surface of the upper electrode film.

6. The device according to claim 1 , wherein

the upper electrode film and the plurality of lower electrode films include tungsten or molybdenum.

7. The device according to claim 1 , further comprising:

a substrate provided below the plurality of lower electrode films;

a plurality of electrode members provided on both sides of a stacked body including the plurality of lower electrode films and the upper electrode film stacked with each other, the plurality of electrode members being connected to the substrate; and

insulating plates each disposed between the stacked body and each of the electrode members, and in contact with the plurality of lower electrode films and the upper electrode film.

8. The device according to claim 7 , further comprising another stacked body provided above the substrate, wherein

the electrode members extend in a first direction crossing the arrangement direction,

one of the electrode members is disposed between the stacked body and the another stacked body,

the another stacked body includes

a plurality of other lower electrode films stacked separated from each other along the arrangement direction, and

another upper electrode film provided above the plurality of other lower electrode films,

each of the lower electrode films and each of the other lower electrode films are electrically connected to each other, and

the upper electrode film and the another upper electrode film are insulated from each other.

9. The device according to claim 7 , further comprising an insulating member provided above the plurality of lower electrode films, extending between the plurality of electrode members in a same direction as the plurality of electrode members, and dividing the upper electrode film.

10. A semiconductor memory device comprising:

a plurality of lower electrode films stacked separated from each other;

an upper electrode film provided above the plurality of lower electrode film;

a semiconductor pillar extending in an arrangement direction of the plurality of lower electrode films and the upper electrode film;

a first insulating film provided between the semiconductor pillar and one of the plurality of lower electrode films and between the semiconductor pillar and the upper electrode film, the first insulating film including a charge trap film; and

a second insulating film provided on a side of a lower surface of the one of the plurality of lower electrode films, on a side of an upper surface of the one of the plurality of lower electrode films, and between the one of the plurality of lower electrode films and the first insulating film, the second insulating film having a composition different from a composition of the first insulating film,

the upper electrode film being in contact with the first insulating film, and the one of the plurality of lower electrode films not being in contact with the first insulating film.

11. The device according to claim 10 , wherein

the first insulating film further includes:

a tunnel film provided between the semiconductor pillar and the charge trap film and containing silicon and oxygen; and

a first insulating layer provided between the charge trap film and the one of the plurality of lower electrode films and between the charge trap film and the upper electrode film, and containing silicon and oxygen,

the charge trap film contains silicon and nitrogen, and

a dielectric constant of the second insulating film is higher than a dielectric constant of the first insulating layer.

12. The device according to claim 10 , wherein

the first insulating film further includes:

a tunnel film provided between the semiconductor pillar and the charge trap film and containing silicon and oxygen,

the charge trap film contains silicon and nitrogen,

the second insulating film includes:

a first insulating layer in contact with the charge trap film and containing silicon and oxygen; and

a second insulating layer provided between the first insulating layer and the one of the plurality of lower electrode films, and

a dielectric constant of the second insulating layer is higher than a dielectric constant of the first insulating layer.

13. The device according to claim 10 , further comprising a metal-containing layer provided on the lower surface of the one of the plurality of lower electrode films, on the upper surface of the one of the plurality of lower electrode films, and between the one of the plurality of lower electrode films and the second insulating film, the metal-containing layer having a composition different from a composition of the plurality of lower electrode films.

Assignments (6)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE POSTAL CODE PREVIOUSLY RECORDED ON REEL 042910 FRAME 0321. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043747/0290 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 042910/0321 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2016
From: FURUMOTO, KAZUHITO; SASAKI, TOSHIYUKI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 038402/0471 →
Continuity (2)
Provisional Application 62266961 · Dec 14, 2015
Related Publication 20170170125A1 · Jun 15, 2017