Memory system
According to one embodiment, a memory system includes a non-volatile memory, a memory interface that performs programming and reading out with respect to the non -volatile memory, a code processor that generates a code word by encoding; and a controller that sets a threshold -voltage read level for determining whether a value of each bit in a received word read out from the non-volatile memory is “0” or “1”. A difference between the number of bits which have value equals “0” and the number of bits which have value equals “1” in the code word depends on a code rate of the encoding. The controller obtains the threshold-voltage read level based on the code rate.
1. A memory system comprising:
a non-volatile memory;
a memory interface that performs programming and reading out with respect to the non-volatile memory;
a code processor that generates a code word by encoding; and
a controller that sets a threshold-voltage read level for determining whether a value of each bit in a received word read out from the non-volatile memory is a first value or a second value, wherein
a difference between the number of bits which have the first value and the number of bits which have the second value in the code word depends on a code rate of the encoding, and
the controller obtains the threshold-voltage read level based on the code rate.
2. The memory system according to claim 1 , wherein
the code processor includes an error mitigating codec that generates an error mitigation code word of which difference between the number of bits which have the first value and the number of bits which have the second value in the error mitigation code word depends on the code rate,
the code word includes the error mitigation code parity part,
the controller inputs the code rate and a coding system that are used in the error mitigating coding to the error mitigating codec,
the error mitigating codec
estimates the number of bits which have the first value and the number of bits which have the second value based on the code rate and the coding system, and
specifies an offset amount from a reference value for a threshold-voltage read level based on the estimated number of bits which have the first value and the estimated number of bits which have the second value, and
the controller obtains the threshold-voltage read level by adjusting the reference value using the offset amount.
3. The memory system according to claim 2 , wherein
the error mitigating codec
generates a first Gaussian function using the estimated number of bits which have the first value, the first Gaussian function representing a first threshold voltage distribution indicating a distribution of threshold voltage levels of memory cells in each of which the first value is programmed,
generates a second Gaussian function using the estimated number of bits which have the second value, the second Gaussian function representing a second threshold voltage distribution indicating a distribution of threshold voltage levels of memory cells in each of which the second value is programmed, and
specifying the offset amount by obtaining a cross-point of the generated first Gaussian function and the generated second Gaussian function.
4. The memory system according to claim 1 , wherein
the code processor includes an error mitigating codec that generates an error mitigation code word of which difference between the number of bits which have the first value and the number of bits which have the second value in the error mitigation code depends on the code rate,
the code word includes the error mitigation code parity part,
the controller inputs the code rate and a coding system that are used in the error mitigating coding to the error mitigating codec,
the error mitigating codec
obtains a first probability that a value of each bit in the code word is the first value and a second probability that a value of each bit in the code word is the second value based on the code rate and the coding system, and
specifies an offset amount from a reference value for a threshold-voltage read level using the obtained first and second probabilities, and
the controller obtains the threshold-voltage read level by adjusting the reference value using the offset amount.
5. The memory system according to claim 4 , wherein
the error mitigating codec
generates a first Gaussian function based on the first probability, the first Gaussian function representing a first threshold voltage distribution indicating a distribution of threshold voltage levels of memory cells in each of which the first value is programmed,
generates a second Gaussian function based on the second probability, the second Gaussian function representing a second threshold voltage distribution indicating a distribution of threshold voltage levels of memory cells in each of which the second value is programmed, and
specifying the offset amount by obtaining a cross-point of the generated first Gaussian function and the generated second Gaussian function.
6. The memory system according to claim 1 , wherein
the code processor includes an error mitigating codec that generates an error mitigation code of which difference between the number of bits which have the first value and the number of bits which have the second value in the error mitigation code depends on the code rate,
the code word includes the error mitigation code parity part,
the controller inputs the code rate and a coding system that are used in the error mitigating coding to the error mitigating codec, and
the error mitigating codec
instructs the memory interface to perform reading out with respect to the non-volatile memory at least four times using different threshold-voltage read levels, respectively,
specifies a threshold voltage level at which a bit error rate of read received word is estimated to be a minimum value using the coding system and the code rate input from the controller and at least four received words obtained by the at least four times of the reading out, and
obtains the specified threshold voltage level as the threshold-voltage read level.
7. The memory system according to claim 1 , wherein
the code processor includes an error mitigating codec that generates an error mitigation code of which difference between the number of bit which have the first value and the number of bit which have the second value in the error mitigation code depends on the code rate,
the code word includes the error mitigation code,
the controller inputs the code rate and a coding system that are used in the error mitigating coding to the error mitigating codec, and
the error mitigating codec
estimates p k as an occurrence frequency or probability of a first value k in the code word and p k+1 as an occurrence frequency or probability of a second value k+1 in the code word based on the code rate and the coding system,
instructs the memory interface to perform reading out with respect to the non-volatile memory at least four times using different threshold-voltage read levels t i , respectively,
solving a following expression (1) using at least four received words obtained by the at least four times of the reading out to specify parameters μ k , σ k , μ k+1 , and σ k+1 in the expression (1),
y
i
=
p
k
×
Q
(
μ
k
-
t
i
σ
k
)
+
p
k
+
1
×
Q
(
μ
k
+
1
-
t
i
σ
k
+
1
)
where
Q
(
x
)
=
∫
x
∞
(
2
π
)
-
1
2
(
e
)
-
t
2
2
dt
,
i
=
1
,
2
,
3
,
4
,
…
(
1
)
specifies a value t that minimizes a bit error rate (BER) represented by a following expression (2) using the specified parameters μ k , σ k , μ k+1 , and σ k+1 , and
BER
(
Vth
)
=
p
k
×
∫
x
∞
(
2
πσ
k
2
)
-
1
2
(
e
)
-
(
t
-
μ
k
)
2
2
σ
k
2
dt
+
p
k
+
1
×
∫
-
∞
x
(
2
πσ
k
+
1
2
)
-
1
2
(
e
)
-
(
t
-
μ
k
+
1
)
2
2
σ
k
+
1
2
dt
(
2
)
obtains the specified value t as the threshold -voltage read level.
8. The memory system according to claim 1 , wherein
the code processor includes an error mitigating codec that generates an error mitigation code of which difference between the number of bit which have the first value and the number of bit which have the second value in the error mitigation code depends on the code rate,
the code word includes the error mitigation code parity part,
the controller inputs the code rate and a coding system that are used in the error mitigating coding to the error mitigating codec, and
the error mitigating codec
instructs the memory interface to perform reading out with respect to the non-volatile memory at least four times using different threshold-voltage read levels, respectively,
specifies a threshold voltage level at which entropy of read received word is estimated to be a maximum value using the coding system and the code rate input from the controller and at least four received words obtained by the at least four times of the reading out, and
obtains the specified threshold voltage level as the threshold-voltage read level.
9. The memory system according to claim 1 , wherein
the code processor includes an error mitigating codec that generates an error mitigation code of which difference between the number of bit which have the first value and the number of bit which have the second value in the error mitigation code depends on the code rate,
the code word includes the error mitigation code parity part,
the controller inputs the code rate and a coding system that are used in the error mitigating coding to the error mitigating codec, and
the error mitigating codec
estimates p k as an occurrence frequency or probability of a first value k in the code word and p k+1 as an occurrence frequency or probability of a second value k+1 in the code word. based on the code rate and the coding system,
instructs the memory interface to perform reading out with respect to the non-volatile memory at least four times using different threshold-voltage read levels t i , respectively,
solving a following expression (1) using at least four received words obtained by the at least four times of the reading out to specify parameters μ k , σ k , μ k+1 , and σ k+1 in the expression (1),
y
i
=
p
k
×
Q
(
μ
k
-
t
i
σ
k
)
+
p
k
+
1
×
Q
(
μ
k
+
1
-
t
i
σ
k
+
1
)
where
Q
(
x
)
=
∫
x
∞
(
2
π
)
-
1
2
(
e
)
-
t
2
2
dt
,
i
=
1
,
2
,
3
,
4
,
…
(
1
)
specifies a value t that maximizes entropy H represented by a following expression (2) using the specified parameters μ k , σ k , μ k+1 , and σ k+1 , and
H
(
Vth
)
=
P
(
state
=
k
|
Vth
)
log
1
P
(
state
=
k
|
Vth
)
+
P
(
state
=
k
+
1
|
Vth
)
log
1
P
(
state
=
k
+
1
|
Vth
)
where
P
(
state
=
k
|
Vth
)
=
P
(
k
)
(
Vth
=
t
)
P
(
k
)
(
Vth
=
t
)
+
P
(
k
+
1
)
(
Vth
=
t
)
,
and
P
(
k
)
(
t
)
=
(
2
πσ
k
2
)
-
1
2
(
e
)
-
(
t
-
μ
k
)
2
2
σ
k
2
(
2
)
obtains the specified value t as the threshold -voltage read level.
10. The memory system according to claim 1 , wherein
the code processor includes
an error mitigating codec that generates an error mitigation code of which difference between the number of bit which have the first value and the number of bit which have the second value is the error mitigation code depends on the code rate, and
an error correction codec that generates the code word by performing error correction coding of data including the error mitigation code generated by the error mitigating codec, and
the memory interface programs the code word generated by the error mitigating codec to the non-volatile memory.