System and method of read/write control for dual channel memory modules for robust performance
View Patent ↗A memory controller for dual-channel DDR DIMMs comprises a first memory channel configured to execute a first memory transaction with a first memory device of a dual-channel DDR DIMM, and a second memory channel configured to execute a second memory transaction with a second memory device of the dual-channel DDR DIMM. The memory controller is configured to determine that the first memory channel is experiencing a degraded performance level in executing the first memory transaction with the first device, and to prevent read-write memory transactions and write-read memory transactions on the first and second memory channels in response to determining that the first memory channel is experiencing the degraded performance level.
1. A memory controller for dual-channel double data rate (DDR) dual in-line memory modules (DIMMs), the memory controller comprising:
a first memory channel configured to execute a first memory transaction with a first memory device of a dual-channel DDR DIMM; and
a second memory channel configured to execute a second memory transaction with a second memory device of the dual-channel DDR DIMM;
wherein the memory controller is configured to:
determine that the first memory channel is experiencing a degraded performance level in executing the first memory transaction with the first device; and
in response to determining that the first memory channel is experiencing the degraded performance level, to prevent read-write memory transactions and write-read memory transactions on the first and second memory channels.
2. The memory controller of claim 1 , wherein, subsequent to determining that the first memory channel is experiencing the degraded performance level, the memory controller is further configured to:
determine that the first memory channel is experiencing a normal performance level in executing a second memory transaction with the first device; and
in response to determining that the first memory channel is experiencing the normal performance level, to allow read-write memory transactions and write-read memory transactions on the first and second memory channels.
3. The memory controller of claim 2 , wherein in determining that the first memory channel is experiencing the degraded performance level, the memory controller is further configured to:
determine a first bit error rate (BER) associated with read memory transactions on the first memory channel; and
determine that the first BER exceeds a BER threshold setting.
4. The memory controller of claim 3 , wherein in determining that the first memory channel is experiencing the normal performance level, the memory controller is further configured to:
determine a second BER associated with the read memory transactions on the first memory channel; and
determine that the second BER is less than the BER threshold setting.
5. The memory controller of claim 2 , wherein in determining that the first memory channel is experiencing the degraded performance level, the memory controller is further configured to:
receive an indication from the dual-channel DDR DIMM that a first bit error rate (BER) associated with write memory transactions on the first memory channel exceeds a BER threshold setting.
6. The memory controller of claim 5 , wherein in determining that the first memory channel is experiencing the normal performance level, the memory controller is further configured to:
receive a second indication from the dual-channel DDR DIMM that a second BER associated with the write memory transactions on the first memory channel is less than the BER threshold setting.
7. The memory controller of claim 2 , wherein in allowing the read-write memory transactions and the write-read memory transactions on the first and second memory channels, the memory controller is further configured to:
wait a predetermined duration between determining that the first memory channel is experiencing the normal performance and allowing the read-write memory transactions and the write-read memory transactions on the first and second memory channels.
8. The memory controller of claim 1 , wherein in further response to determining that the first memory channel is experiencing the degraded performance level, the memory controller is further configured to:
allow read-read memory transactions, read-idle memory transactions, write-write memory transactions, and write-idle memory transactions on the first and second memory channels.
9. A method for controlling dual-channel double data rate (DDR) dual in-line memory modules (DIMMs), the method comprising:
configuring a first memory channel of a memory controller to execute a first memory transaction with a first memory device of a dual-channel DDR DIMM;
configuring a second memory channel of the memory controller to execute a second memory transaction with a second memory device of the dual-channel DDR DIMM;
determining, by the memory controller, that the first memory channel is experiencing a degraded performance level in executing the first memory transaction with the first device; and
preventing, by the memory controller, read-write memory transactions and write-read memory transactions on the first and second memory channels in response to determining that the first memory channel is experiencing the degraded performance level.
10. The method of claim 9 , further comprising:
determining, by the memory controller, that the first memory channel is experiencing a normal performance level in executing a second memory transaction with the first device subsequent to determining that the first memory channel is experiencing the degraded performance level; and
allowing, by the memory controller, read-write memory transactions and write-read memory transactions on the first and second memory channels in response to determining that the first memory channel is experiencing the normal performance level.
11. The method of claim 10 , wherein in determining that the first memory channel is experiencing the degraded performance level, the method further comprises:
determining, by the memory controller, a first bit error rate (BER) associated with read memory transactions on the first memory channel; and
determining, by the memory controller, that the first BER exceeds a BER threshold setting.
12. The method of claim 11 , wherein in determining that the first memory channel is experiencing the normal performance level, the method further comprises:
determining, by the memory controller, a second BER associated with the read memory transactions on the first memory channel; and
determining, by the memory controller, that the second BER is less than the BER threshold setting.
13. The method of claim 9 , wherein in determining that the first memory channel is experiencing the degraded performance level, the method further comprises:
receiving an indication from the dual-channel DDR DIMM that a first bit error rate (BER) associated with write memory transactions on the first memory channel exceeds a BER threshold setting.
14. The method of claim 13 , wherein in determining that the first memory channel is experiencing the normal performance level, the method further comprises:
receiving a second indication from the dual-channel DDR DIMM that a second BER associated with the write memory transactions on the first memory channel is less than the BER threshold setting.
15. The method of claim 10 , wherein in allowing the read-write memory transactions and the write-read memory transactions on the first and second memory channels, the method further comprises:
waiting a predetermined duration between determining that the first memory channel is experiencing the normal performance and allowing the read-write memory transactions and the write-read memory transactions on the first and second memory channels.
16. The method of claim 9 , wherein in further response to determining that the first memory channel is experiencing the degraded performance level, the method further comprises:
allowing, by the memory controller, read-read memory transactions, read-idle memory transactions, write-write memory transactions, and write-idle memory transactions on the first and second memory channels.
17. An information handling system, comprising:
a dual-channel double data rate (DDR) dual in-line memory module (DIMM); and
a memory controller for dual-channel DDR DIMMs, the memory controller including a first memory channel configured to execute a first memory transaction with a first memory device of the dual-channel DDR DIMM, and a second memory channel configured to execute a second memory transaction with a second memory device of the dual-channel DDR DIMM, wherein the memory controller is configured to:
determine that the first memory channel is experiencing a degraded performance level in executing the first memory transaction with the first device; and
in response to determining that the first memory channel is experiencing the degraded performance level, to prevent read-write memory transactions and write-read memory transactions on the first and second memory channels.
18. The information handling system of claim 17 , wherein, subsequent to determining that the first memory channel is experiencing the degraded performance level, the memory controller is further configured to:
determine that the first memory channel is experiencing a normal performance level in executing a second memory transaction with the first device; and
in response to determining that the first memory channel is experiencing the normal performance level, to allow read-write memory transactions and write-read memory transactions on the first and second memory channels.
19. The information handling system of claim 18 , wherein in determining that the first memory channel is experiencing the degraded performance level, the memory controller is further configured to:
determine a first bit error rate (BER) associated with read memory transactions on the first memory channel; and
determine that the first BER exceeds a BER threshold setting.
20. The information handling system of claim 19 , wherein in determining that the first memory channel is experiencing the normal performance level, the memory controller is further configured to:
determine a second BER associated with the read memory transactions on the first memory channel; and
determine that the second BER is less than the BER threshold setting.