Integrated circuit devices and methods of manufacturing the same

1. A method of manufacturing an integrated circuit device, the method comprising:

forming a preliminary fin-shaped active region by partially etching a substrate;

forming an insulating layer covering a lower, portion of the preliminary fin-shaped active region such that an upper portion of the preliminary fin-shaped active region protrudes above the insulating layer;

forming a fin-shaped active region and a hydrogen atomic layer by annealing the protruding portion of the preliminary fin-shaped active region in a hydrogen atmosphere, the fin-shaped active region having a smoother surface than a surface of the preliminary fin-shaped active region and the hydrogen atomic layer covering the surface of the fin-shaped active region;

forming a gate insulation layer on the hydrogen atomic layer to cover a top surface and opposite sidewalls of the fin-shaped active region; and

forming a gate electrode on the gate insulation layer to cover the top surface and the opposite sidewalls of the fin-shaped active region.

2. The method of claim 1 , wherein forming a fin-shaped active region and a hydrogen atomic layer is performed such that the fin-shaped active region has the surface terminated with hydrogen atoms constituting the hydrogen atomic layer.

3. The method of claim 1 , wherein forming a fin-shaped active region comprises changing morphology of a surface of the protruding portion of the preliminary fin-shaped active region during the annealing in the hydrogen atmosphere.

4. The method of claim 1 , wherein forming a fin-shaped active region comprises reducing a roughness of a surface of the protruding portion of the preliminary fin-shaped active region using a hydrogen-enhanced surface atom migration on the surface of the protruding portion of the preliminary fin-shaped active region during the annealing in the hydrogen atmosphere.

5. The method of claim 1 , wherein forming a fin-shaped active region further comprises removing contaminants from a surface of the protruding portion of the preliminary fin-shaped active region using the annealing in the hydrogen atmosphere.

6. The method of claim 1 :

wherein forming a gate insulation layer comprises forming a lower gate insulation layer contacting the hydrogen atomic layer; and

wherein forming a lower gate insulation layer comprises:

forming an oxide layer on the hydrogen atomic layer by a first oxidation treatment using a plasma; and

increasing a thickness of the oxide layer by a second oxidation treatment that does not use a plasma in a state in which the hydrogen atomic layer is covered with the oxide layer.

7. The method of claim 6 , wherein forming an oxide layer comprises forming the oxide layer in a plasma atmosphere using an oxygen (O 2 ) gas and an inert gas.

8. The method of claim 6 , wherein forming an oxide layer comprises forming the oxide layer in a plasma atmosphere using an oxygen (O 2 ) gas, an inert gas and a hydrogen (H 2 ) gas.

9. The method of claim 6 , wherein increasing a thickness of the oxide layer comprises performing an in-situ steam generation (ISSG) process using steam, or a combination of a hydrogen (H 2 ) gas and an oxygen (O 2 ) gas.

10. The method of claim 6 , further comprising, after the forming an oxide layer, prior to the increasing a thickness of the oxide layer, decreasing the thickness of the oxide layer by partially removing the oxide layer without any exposure of the fin-shaped active region disposed thereunder.

11. The method of claim 10 , wherein decreasing the thickness of the oxide layer comprises decreasing the oxide layer using a wet etching process.

12. The method of claim 6 , wherein forming a lower gate insulation layer comprises forming a silicon oxynitride layer by nitriding at least a portion of the oxide layer.

13. The method of claim 12 , wherein nitriding at least a portion of the oxide layer comprises nitriding at least a portion of the oxide layer after increasing a thickness of the oxide layer.

14. The method of claim 12 , wherein nitriding at least a portion of the oxide layer comprises nitriding at least a portion of the oxide layer using a decoupled plasma nitridation (DPN) process.

15. The method of claim 6 , wherein forming the gate insulation layer further comprises:

forming an interface layer covering the lower gate insulation layer; and

forming a high-k dielectric layer on the interface layer and having a dielectric constant greater than a dielectric constant of each of the lower gate insulation layer and the interface layer.

16. A method of manufacturing an integrated circuit device, the method comprising:

forming first and second preliminary fin-shaped active regions protruding in first and second regions of a substrate, respectively, by partially etching the substrate;

forming an insulating layer covering respective lower portions of the first and second preliminary fin-shaped active regions such that respective upper portions of the first and second preliminary fin-shaped active regions protrudes above the insulating layer;

forming a first fin-shaped active region having a surface with a smoothness greater than a smoothness of a surface of the first preliminary fin-shaped active region in the first region and a second fin-shaped active region having a surface with a smoothness greater than a smoothness of a surface of the second preliminary fin-shaped active region in the second region by annealing the respective protruding portions of the first and second preliminary fin-shaped active regions in a hydrogen atmosphere;

after the annealing in the hydrogen atmosphere, without a wet process, forming a first lower gate insulation layer covering a top surface and opposite sidewalls of the first fin-shaped active region in the first region and a second lower gate insulation layer covering a top surface and opposite sidewalls of the second fin-shaped active region in the second region;

exposing an upper portion of the second fin-shaped active region by removing the second lower gate insulation layer in the second region; and

forming a first high-k dielectric layer on the first lower gate insulation layer in the first region and a second high-k dielectric layer on the second fin-shaped active region in the second region.

17. The method of claim 16 , wherein the forming first and second fin-shaped active regions comprises forming a hydrogen atomic layer covering respective surfaces of the first and second fin-shaped active regions during annealing in the hydrogen atmosphere.

18. The method of claim 17 , wherein each of the first and second fin-shaped active regions is formed to have a surface that is terminated with hydrogen atoms constituting the hydrogen atomic layer.

19. The method of claim 16 , further comprising:

reducing a roughness of a surface of the protruding portion of each of the first and second preliminary fin-shaped active regions using a hydrogen-enhanced surface atom migration on the surface of the protruding portion of each of the first and second preliminary fin-shaped active regions during the annealing in the hydrogen atmosphere.

20. The method of claim 16 , wherein forming first and second lower gate insulation layers comprises:

forming an oxide layer on the first and second fin-shaped active regions by a first oxidation treatment using a plasma in the first and second regions; and

increasing a thickness of the oxide layer by a second oxidation treatment that does not use a plasma in the first and second regions.