IP Library Granted Patent US 9,780,111
Granted Patent B2
US 9,780,111 · App. 14/828,830 · Granted Oct 3, 2017

Semiconductor device and method for manufacturing the same

Inventors: Takeshi Ishizaki (Aichi, JP); Junichi Wada (Mie, JP); Atsuko Sakata (Mie, JP); Kei Watanabe (Mie, JP); Masayuki Kitamura (Mie, JP); Daisuke Ikeno (Mie, JP); Satoshi Wakatsuki (Mie, JP); Hirotaka Ogihara (Mie, JP); Shinya Okuda (Oita, JP)
Assignee: Toshiba Memory Corporation
H01L27/11582H01L27/1157
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Quick Facts
Patent No.
US 9,780,111
App. No.
14/828,830
Granted
Oct 3, 2017
Kind
B2
Abstract

According to one embodiment, a semiconductor device includes a substrate, a stacked body, a film having semi-conductivity or conductivity, and a memory film. The stacked body includes a plurality of metal layers, a plurality of insulating layers, and a plurality of intermediate layers stacked on a major surface of the substrate. The film extends in the stacked body in a stacking direction of the stacked body. The memory film is provided between the film and the metal layers. The metal layers are tungsten layers and the intermediate layers are tungsten nitride layers. Or the metal layers are molybdenum layers and the intermediate layers are molybdenum nitride layers.

Claims (30)

1. A semiconductor device comprising:

a substrate;

a stacked body including a plurality of metal layers, a plurality of insulating layers, and a plurality of intermediate layers stacked on a major surface of the substrate;

a film having semi-conductivity or conductivity extending in the stacked body in a stacking direction of the stacked body; and

a memory film provided between the film and the metal layers,

the metal layers being tungsten layers and the intermediate layers being tungsten nitride layers, or the metal layers being molybdenum layers and the intermediate layers being molybdenum nitride layers,

the intermediate layer being provided between a lower surface of the metal layer and the insulating layer, the intermediate layer being not provided between an upper surface of the metal layer and the insulating layer, and the intermediate layer being in contact with the metal layer.

2. The device according to claim 1 , wherein the intermediate layers are separated from each other in the stacking direction of the stacked body.

3. A semiconductor device comprising:

a substrate;

a stacked body including a plurality of metal layers, a plurality of insulating layers, and a plurality of intermediate layers stacked on a major surface of the substrate;

a film having semi-conductivity or conductivity extending in the stacked body in a stacking direction of the stacked body; and

a memory film provided between the film and the metal layers,

the metal layers being tungsten layers and the intermediate layers being tungsten nitride layers, or the metal layers being molybdenum layers and the intermediate layers being molybdenum nitride layers,

the intermediate layer being provided between an upper surface of the metal layer and the insulating layer, the intermediate layer being not provided between a lower surface of the metal layer and the insulating layer, and the intermediate layer being in contact with the metal layer.

4. The device according to claim 3 , wherein the intermediate layers are separated from each other in the stacking direction of the stacked body.

5. A semiconductor device comprising:

a substrate;

a stacked body including a plurality of metal layers, a plurality of insulating layers, and a plurality of intermediate layers stacked on a major surface of the substrate, a number of the intermediate layers being smaller than a number of the metal layers, a direction of an internal stress of the metal layer along the major surface of the substrate and a direction of an internal stress of the intermediate layer along the major surface of the substrate being opposite;

a film having semi-conductivity or conductivity extending in the stacked body in a stacking direction of the stacked body; and

a memory film provided between the film and the metal layers.

6. The device according to claim 5 , wherein

(an internal stress of the metal layer×a film thickness of the metal layer×a total number of the metal layers)+(an internal stress of the insulating layer×a film thickness of the insulating layer×a total number of the insulating layers)+(an internal stress of the intermediate layer×a film thickness of the intermediate layer×a total number of the intermediate layer) is smaller than 1700000 [MPa·nm].

7. The device according to claim 5 , wherein the intermediate layers have conductivity.

8. The device according to claim 5 , wherein the intermediate layers contain metal nitride.

9. The device according to claim 5 , wherein the metal layers are tungsten layers and the intermediate layers are tungsten nitride layers, or the metal layers are molybdenum layers and the intermediate layers are molybdenum nitride layers.

10. The device according to claim 5 , wherein the intermediate layer is provided between the metal layer and the insulating layer, and is in contact with the metal layer.

11. The device according to claim 10 , wherein the intermediate layer is provided between a lower surface of the metal layer and the insulating layer, and the intermediate layer is not provided between an upper surface of the metal layer and the insulating layer.

12. The device according to claim 10 , wherein the intermediate layer is provided between an upper surface of the metal layer and the insulating layer, and the intermediate layer is not provided between a lower surface of the metal layer and the insulating layer.

13. The device according to claim 5 , wherein the intermediate layer is provided between the insulating layers, and an upper surface of the intermediate layer and a lower surface of the intermediate layer are in contact with the respective insulating layers.

Assignments (6)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE POSTAL CODE PREVIOUSLY RECORDED ON REEL 042910 FRAME 0321. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043747/0290 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 042910/0321 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2015
From: ISHIZAKI, TAKESHI; WADA, JUNICHI; SAKATA, ATSUKO; WATANABE, KEI; KITAMURA, MASAYUKI; IKENO, DAISUKE; WAKATSUKI, SATOSHI; OGIHARA, HIROTAKA; OKUDA, SHINYA
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 036433/0499 →
Priority Claims (1)
JP 2015-078949 · Apr 8, 2015 · national
Continuity (1)
Related Publication 20160300845A1 · Oct 13, 2016