System and method for synchronization among multiple PLL-based clock signals
A method synchronizes clock signals generated by a system that includes multiple PLLs that are connected in parallel and output frequency dividers driven by the PLLs. The system receives a common frequency reference signal and a common synchronization signal. Each PLL may have a reference signal frequency divider. The reference frequency divider may be phase-reset, for example, by a transition to a first logic state in the synchronization signal, and the output frequency dividers are each phase-reset, for example, by a transition to a second logic state following the transition to the first logic state in the synchronization signal. The transition to the first logic state may be, for example, a rising edge.
1. A clock generation system receiving a reference frequency signal and a synchronization signal having a first logic state and a second logic state, comprising a plurality of clock generators connected in parallel to receive the reference frequency signal, wherein each clock generator comprises:
a reference frequency divider which receives the reference frequency signal and provides a frequency-divided reference signal;
a phase-locked loop which receives the frequency-divided reference signal and provides a phase-locked signal that is phase-locked to the frequency-divided reference signal; and
an output frequency divider that receives the phase-locked signal and provides an output signal of a predetermined frequency that is a function of the frequency of the reference frequency signal, wherein the reference frequency divider is phase-reset by a transition to the first logic state in the synchronization signal, and wherein the output frequency divider is phase-reset by a transition to the second logic state following the transition to the first logic state in the synchronization signal.
2. The clock generation system of claim 1 , wherein the transition to the first logic state is a rising edge.
3. The clock generation system of claim 1 , wherein the phase-locked loop comprises a voltage controlled oscillator and a feedback frequency divider.
4. The clock generation system of claim 1 , wherein the output frequency dividers of the clock generation system are provided without cascading frequency dividers.
5. A method for clock generation, comprising:
providing a reference frequency signal and a synchronization signal having a first logic state and a second logic state; and
connecting a plurality of clock generators in parallel to receive the reference frequency signal, wherein each clock generator is provided according to the steps:
providing a reference frequency divider which receives the reference frequency signal and provides a frequency-divided reference signal, the reference frequency divider provided to be phase-reset by a transition to the first logic state in the synchronization signal;
providing a phase-locked loop which receives the frequency-divided reference signal and provides a phase-locked signal that is phase-locked to the frequency-divided reference signal; and
providing an output frequency divider that receives the phase-locked signal and provides an output signal of a predetermined frequency that is a function of the frequency of the reference frequency signal, the output frequency divider being provided to be phase-reset by a transition to the second logic state following the transition to the first logic state in the synchronization signal.
6. The method of claim 5 , wherein the transition to the first logic state is a rising edge.
7. The method of claim 5 , wherein the function is a multiple or a fraction.
8. The method of claim 5 , wherein the phase-locked loop comprises a voltage controlled oscillator and a feedback frequency divider.
9. The method of claim 5 , wherein the output frequency dividers of the clock generators are provided without cascading frequency dividers.