IP Library Granted Patent US 9,823,731
Granted Patent B2
US 9,823,731 · App. 14/724,943 · Granted Nov 21, 2017

Adaptive power control of address map memory devices

Inventors: Nathaniel G. Burke (Hillsboro, OR); Sanjeev N. Trika (Portland, OR)
Assignee: Intel Corporation
G06F1/3287G06F1/32G06F1/3212G06F1/3225G06F1/3268G06F1/3275G06F3/0625G06F3/0634G06F3/0688G06F12/02G06F12/0246G06F12/0638G11C7/1072G06F3/0631G06F12/0607G06F2212/1028G06F2212/205G06F2212/7201G06F2212/7208Y02B60/1225Y02B60/1228Y02B60/1246
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Quick Facts
Patent No.
US 9,823,731
App. No.
14/724,943
Granted
Nov 21, 2017
Kind
B2
Abstract

An apparatus includes a storage resource to store data. The data can be accessible by a host computer system. The apparatus includes a set of dynamically powered volatile memory devices that are configured to store mapping information. The mapping information maps logical addresses of received access requests to corresponding physical addresses of the storage resource to which the access requests pertain. In accordance with received mode setting information, the controller logic adaptively controls power settings of the volatile memory devices storing the mapping information. If an abundance of power such as 120 VAC power is available, more of volatile memory devices can be powered to store a greater portion of the mapping information. If only battery power is available, fewer than all of the volatile memory devices can be powered to store a smaller portion of the mapping information.

Claims (50)

1. An apparatus comprising:

multiple dynamically powered volatile memory devices to store state information;

control logic operable to:

receive mode setting information;

adaptively control power settings of the volatile memory devices depending on the mode setting information; and

wherein the state information is address mapping information mapping logical addresses of received access requests to corresponding physical addresses of a storage resource to which the received access requests pertain.

2. The apparatus as in claim 1 , wherein the control logic dynamically adjusts how many of the volatile memory devices are powered depending on a type of power that is provided to power the multiple dynamically powered volatile memory devices.

3. The apparatus as in claim 1 , wherein the control logic dynamically adjusts how many of the volatile memory devices are powered depending on a source providing power to the volatile memory devices.

4. The apparatus as in claim 1 , wherein the storage resource is a solid state drive including multiple non-volatile memory devices to store data; and

wherein the address mapping information stored in the volatile memory devices includes a mapping of the logical addresses to the corresponding physical address of the multiple non-volatile memory devices.

5. The apparatus as in claim 1 further comprising:

multiple non-volatile memory devices, a portion of the multiple non-volatile memory devices allocated to store an original copy of the state information; and

wherein the dynamically powered volatile memory devices at least temporarily store at least a portion of a copy of the state information stored in the portion of the multiple non-volatile memory devices.

6. The apparatus as in claim 1 , wherein the control logic, as specified by first received mode setting information, is operable to power all of the volatile memory devices for storage of a first amount of state information; and

wherein the control logic, as specified by second received mode setting information to reduce power consumption with respect to the first mode setting information, is operable to depower at least one but fewer than all of the volatile memory devices for storage of a second amount of state information, the second amount of state information less than the first amount of state information.

7. The apparatus as in claim 1 , wherein the adaptive control of the power settings changes a capacity of available memory in the volatile memory devices to store the state information.

8. The apparatus as in claim 1 further comprising:

host processor hardware operable to receive access requests to the storage resource; and

an access controller operable to receive the access requests from the host processor hardware, the access controller utilizing the state information in the dynamically powered volatile memory devices to access the corresponding physical addresses of the storage resource to which the access requests pertain.

9. The apparatus as in claim 1 , wherein the control logic is operable to control retrieval and storage of the state information in the volatile memory devices depending at least in part on the received mode setting information.

10. The apparatus as in claim 9 , wherein the control logic is operable to set at least one of the volatile memory devices to operate in a paging mode during a first power mode in which fewer than all but at least one of the volatile memory devices is powered to store the address mapping information; and

wherein the control logic is operable to set the volatile memory devices to operate in a non-paging mode during a second power mode in which all of the volatile memory devices are powered to store the address mapping information.

11. The apparatus as in claim 1 , wherein the control logic is operable to set at least one of the volatile memory devices in a standby mode to reduce power consumption of the at least one volatile memory device in response to occurrence of a condition in which the state information stored in the at least one volatile memory device has not been accessed for a threshold amount of time.

12. The apparatus as in claim 1 , wherein the control logic, as specified by first received mode setting information, powers a first portion of the volatile memory devices for storage of up to a first amount of the state information; and

wherein the control logic, as specified by second received mode setting information, powers a second portion of the volatile memory devices for storage of a second amount of the state information;

wherein the second portion is greater than the first portion; and

wherein the second amount of the state information is greater than the first amount of the state information.

13. The apparatus as in claim 12 , wherein the control logic is operable to initiate depowering of at least one currently powered volatile memory device in response to detecting a decrease in an availability of power to power the volatile memory devices.

14. The apparatus as in claim 1 , wherein the control logic dynamically adjusts how many of the volatile memory devices are powered depending on an availability of power.

15. The apparatus as in claim 14 , wherein the control logic is operable to initiate powering of an additional one of the volatile memory devices in response to detecting an increase in an availability of power to power the volatile memory devices.

16. A computer system including the apparatus in claim 1 , the computer system further comprising:

a display screen on which to render an image based at least in part on using the state information to access data stored in the storage resource.

17. The computer system as in claim 16 , wherein the storage resource is a solid state drive to which the computer system has access through an access controller, the access controller utilizing the state information to service access requests.

18. A method comprising:

initiating storage of state information in a set of multiple volatile memory devices including at least one powered volatile memory storage device, the state information facilitating access to data in a storage resource;

receiving mode setting information;

adaptively powering the set of multiple volatile memory devices in accordance with the mode setting information; and

wherein adaptively powering the multiple volatile memory devices varies an amount of storage space that is available to store the state information.

19. The method as in claim 18 further comprising:

accessing a full copy of the state information from a non-volatile repository; and

varying a portion of the full copy of the state information to retrieve from the non-volatile repository and store in the set of multiple volatile memory devices depending on how many of the multiple volatile memory devices in the set are powered.

20. The method as in claim 18 , wherein the received mode setting information indicates to increase a number of the volatile memory devices in the set that are powered; and

wherein adaptively powering the set of multiple volatile memory devices includes increasing a number of the volatile memory devices that are powered in the set in accordance with the received mode setting information.

21. The method as in claim 18 , wherein the received mode setting information indicates to decrease a number of the volatile memory devices in the set that are currently powered; and

wherein adaptively powering the set of multiple volatile memory devices includes decreasing a number of the volatile memory devices that are powered in the set in accordance with the received mode setting information.

22. Computer-readable storage hardware having instructions stored thereon, the instructions, when carried out by computer processor hardware, cause the computer processor hardware to perform operations of:

storing state information in volatile memory storage hardware, the state information facilitating access to a storage resource;

receiving mode setting information; and

adaptively controlling power to portions of the volatile memory storage hardware in accordance with the mode setting information, the adaptively controlling including dynamically adjusting power to the volatile memory storage hardware depending on a source providing power to the volatile memory storage hardware.

23. The computer readable storage hardware as in claim 22 , wherein adaptively controlling power to the volatile memory storage hardware varies an amount of storage space that is available to store the state information.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072915/0599 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2017
From: BURKE, NATHANIEL G.; TRIKA, SANJEEV N.
To: INTEL CORPORATION
Reel/Frame 042528/0006 →
Continuity (2)
Division 13688546 · Nov 29, 2012
Related Publication 20150261289A1 · Sep 17, 2015