Method for preparing a system for a power loss

1. A system, comprising:

a power management unit including a timer circuit, wherein the power management unit is configured to:

generate a power supply voltage at a first voltage level corresponding to a first mode of the system in which a first set of functions are implemented;

change a state of a status signal in response to a detection of an event;

maintain the power supply voltage at the first voltage level;

initiate the timer circuit in response to the detection of the event; and

reduce the power supply voltage from the first voltage level to a second, non-zero voltage level in response to a determination that a count value of the timer circuit has reached a threshold value, wherein the second, non-zero voltage level corresponds to a second mode of the system in which a subset of the first set of functions is implemented;

a non-volatile memory;

a volatile memory; and

a processor configured to:

transition from a first operating mode to a second operating mode in response to a determination that the state of the status signal has changed; and

cancel pending commands to the non-volatile memory in response to the transition to the second operating mode;

wherein the non-volatile memory is configured to complete active commands prior to the count value of the timer circuit reaching the threshold value; and

wherein the processor is further configured to send a command to instruct the volatile memory to enter a low power mode in response to a determination that the non-volatile memory has completed the active commands.

2. The system of claim 1 , wherein the processor is further configured to:

access data in the volatile memory; and

send the accessed data to the non-volatile memory to allow the non-volatile memory to complete the active commands.

3. The system of claim 1 , wherein the processor is further configured to transition to a reset state in response to the reduction of the power supply voltage.

4. The system of claim 1 , wherein the power management unit is further configured to change the state of the status signal in response to an assertion of a reset signal.

5. The system of claim 1 , wherein the power management unit is further configured to change the state of the status signal in response to a determination that a voltage level of a power supply input is less than a threshold level.

6. The system of claim 1 , wherein the power management unit is further configured to change the state of the status signal in response to a determination that an operating temperature is greater than a threshold temperature.

7. The system of claim 1 , wherein the processor is further configured to send a power down command to a display in response to the determination the state of the status signal has changed.

8. A method for operating a computing system, the method comprising:

generating a power supply voltage at a first voltage level corresponding to a first mode of the computing system in which a first set of functions are implemented;

transitioning at least a portion of the computing system from a first operating state to a second operating state in response to a detection of an event;

maintaining the power supply voltage at the first voltage level;

initiating a timer circuit in response to the detection of the event;

changing a voltage level of a power supply from the first voltage level to a second, non-zero voltage level in response to a determination that a count value of the timer circuit has reached a threshold value, wherein the second, non-zero voltage level corresponds to a second mode of the computing system in which a subset of the first set of functions is implemented;

cancelling pending commands for a non-volatile memory in response to the transition to the second operating state;

completing active commands for the non-volatile memory prior to the count value of the timer circuit reaching the threshold value; and

sending a command to instruct a volatile memory to enter a low power mode in response to determining that the active commands have completed.

9. The method of claim 8 , wherein completing the active commands comprises:

accessing data in the volatile memory; and

sending the accessed data to the non-volatile memory.

10. The method of claim 8 , further comprising transitioning, the at least a portion of the computing system, to a reset state in response to determining that the count value of the timer circuit has reached the threshold value.

11. The method of claim 8 , wherein the event corresponds to a determination that a reset signal has been asserted.

12. The method of claim 8 , wherein the event corresponds to a determination that a voltage level of a power supply signal is less than a threshold level.

13. The method of claim 8 , wherein the event corresponds to a determination that an operating temperature is greater than a threshold temperature.

14. The method of claim 8 , further comprising sending a power down command to a display in response to detecting the event.

15. An apparatus, comprising:

a non-volatile memory controller coupled to a non-volatile memory;

a network interface coupled to one or more computing devices via a network;

a communication interface coupled to a power management unit, wherein the power management unit includes a timer circuit;

a volatile memory controller coupled to a volatile memory; and

a processor core configured to:

send, via the communication interface, a command to set a value in the timer circuit, wherein the value in the timer circuit corresponds to a threshold period of time;

transition from a first operating state to a second operating state in response to a detection of a change in a state of a status signal;

interrupt an active data exchange between the network interface and at least one computing device in response to the transition from the first operating state to the second operating state; and

transition from the second operating state to an inactive off state in response to a determination that the threshold period of time has elapsed since detecting the change in the state of the status signal;

wherein the non-volatile memory controller is configured to send a cancel command to the non-volatile memory in response to the detection of the change in the state of the status signal, wherein the cancel command instructs the non-volatile memory to complete an active command and cancel pending commands; and

wherein the volatile memory controller is configured to send a low power command to the volatile memory in response to receiving an indication from the non-volatile memory controller that the active command in the non-volatile memory has completed.

16. The apparatus of claim 15 , wherein the processor core is further configured to set the value in the timer circuit such that the threshold period of time allows the non-volatile memory sufficient time to complete the active command.

17. The apparatus of claim 15 , wherein the volatile memory controller is further configured to access data in the volatile memory, and wherein the non-volatile memory controller is further configured to send the accessed data to the non-volatile memory to allow the non-volatile memory to complete the active command.

18. The apparatus of claim 15 , wherein the pending commands include one or more program commands or erase commands.

19. The apparatus of claim 17 , wherein the low power command activates a reduced power mode in the volatile memory.

20. The apparatus of claim 15 , wherein the processor core is further configured to send a power down command to a display in response to the detection of the change in the state of the status signal.