Reducing power consumption in a multi-slice computer processor
Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.
1. A multi-slice computer processor that includes a re-order buffer, the multi-slice computer processor configured for:
designating an entry in the re-order buffer as being invalid and unwritten;
assigning a pending instruction to the entry in the re-order buffer;
responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid;
writing data generated by executing the pending instruction into the re-order buffer; and
responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.
2. The multi-slice computer processor of claim 1 wherein the multi-slice computer processor is further configured for:
receiving a request to read the entry in the re-order buffer;
determining whether the entry in the re-order buffer is designated as being valid and written;
responsive to determining that the entry in the re-order buffer is designated as being valid and written, servicing the request to read the entry in the re-order buffer; and
responsive to determining that the entry in the re-order buffer is not designated as being valid and written, dismissing the request to read the entry in the re-order buffer.
3. The multi-slice computer processor of claim 1 wherein the multi-slice computer processor further comprises an architected register file and the multi-slice computer processor is further configured for:
receiving a request to read an entry in the architected register file;
determining whether the entry in the re-order buffer is designated as being valid;
responsive to determining that the entry in the re-order buffer is designated as being valid, dismissing the request to read the entry in the architected register file; and
responsive to determining that the entry in the re-order buffer is not designated as being valid, servicing the request to read the entry in the architected register file.
4. The multi-slice computer processor of claim 1 wherein the multi-slice computer processor further comprises an architected register file and the multi-slice computer processor is further configured for:
detecting that the pending instruction has executed; and
responsive to detecting that the pending instruction has executed, moving the entry in the re-order buffer to the architected register file.
5. The multi-slice computer processor of claim 4 wherein the multi-slice computer processor is further configured for, responsive to moving the entry in the re-order buffer to the architected register file, designating the entry in the re-order buffer as being invalid and unwritten.
6. The multi-slice computer processor of claim 1 wherein the multi-slice computer processor further comprises an architected register file and the multi-slice computer processor is further configured for:
dispatching the pending instruction, the pending instruction identifying an entry in the re-order buffer that includes an operand for the pending instruction;
determining whether the entry in the re-order buffer that includes the operand for the pending instruction is valid and written or valid and unwritten;
responsive to determining that the entry in the re-order buffer that includes the operand for the pending instruction is valid and written, reading the operand from the reorder buffer; and
responsive to determining that the entry in the re-order buffer that includes the operand for the pending instruction is valid and unwritten, reading the operand from the architected register file.
7. The multi-slice computer processor of claim 1 wherein each entry in the re-order buffer includes a valid bit and a reorder bit.
8. A computing system, the computing system including a multi-slice computer processor that includes a re-order buffer, the multi-slice computer processor configured for:
designating an entry in the re-order buffer as being invalid and unwritten;
assigning a pending instruction to the entry in the re-order buffer;
responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid;
writing data generated by executing the pending instruction into the re-order buffer; and
responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.
9. The computing system of claim 8 wherein the multi-slice computer processor is further configured for:
receiving a request to read the entry in the re-order buffer;
determining whether the entry in the re-order buffer is designated as being valid and written;
responsive to determining that the entry in the re-order buffer is designated as being valid and written, servicing the request to read the entry in the re-order buffer; and
responsive to determining that the entry in the re-order buffer is not designated as being valid and written, dismissing the request to read the entry in the re-order buffer.
10. The computing system of claim 8 wherein the multi-slice computer processor further comprises an architected register file and the multi-slice computer processor is further configured for:
receiving a request to read an entry in the architected register file;
determining whether the entry in the re-order buffer is designated as being valid;
responsive to determining that the entry in the re-order buffer is designated as being valid, dismissing the request to read the entry in the architected register file; and
responsive to determining that the entry in the re-order buffer is not designated as being valid, servicing the request to read the entry in the architected register file.
11. The computing system of claim 8 wherein the multi-slice computer processor further comprises an architected register file and the multi-slice computer processor is further configured for:
detecting that the pending instruction has executed; and
responsive to detecting that the pending instruction has executed, moving the entry in the re-order buffer to the architected register file.
12. The computing system of claim 11 wherein the multi-slice computer processor is further configured for, responsive to moving the entry in the re-order buffer to the architected register file, designating the entry in the re-order buffer as being invalid and unwritten.
13. The computing system of claim 8 wherein each entry in the re-order buffer includes a valid bit and a reorder bit.
14. The computing system of claim 8 wherein the multi-slice computer processor further comprises an architected register file and the multi-slice computer processor is further configured for:
dispatching the pending instruction, the pending instruction identifying an entry in the re-order buffer that includes an operand for the pending instruction;
determining whether the entry in the re-order buffer that includes the operand for the pending instruction is valid and written or valid and unwritten;
responsive to determining that the entry in the re-order buffer that includes the operand for the pending instruction is valid and written, reading the operand from the reorder buffer; and
responsive to determining that the entry in the re-order buffer that includes the operand for the pending instruction is valid and unwritten, reading the operand from the architected register file.