Stacked semiconductor chip RGBZ sensor
An apparatus is described that includes a first semiconductor chip having a first pixel array. The first pixel array has visible light sensitive pixels. The apparatus includes a second semiconductor chip having a second pixel array. The first semiconductor chip is stacked on the second semiconductor chip such that the second pixel array resides beneath the first pixel array. The second pixel array has IR light sensitive pixels for time-of-flight based depth detection.
1. An apparatus, comprising:
a first semiconductor chip having a first pixel array, said first pixel array having visible light sensitive pixels; and,
a second semiconductor chip having a second pixel array, said first semiconductor chip stacked on said second semiconductor chip such that said second pixel array resides beneath said first pixel array, said second pixel array having IR light sensitive pixels for time-of-flight based depth detection, wherein, an IR sensitive pixel resides directly beneath one or more of the visible light sensitive pixels such that incident IR light received by the IR sensitive pixel passes through the one or more visible light pixels, and wherein, first interconnect metallization of the first semiconductor chip faces second interconnect metallization of the second semiconductor chip only outside respective surface areas of the first pixel array and the second pixel array where frontside light guide structures of the first pixel array and frontside light guide structures of the second pixel array couple incident light that flows through the visible light sensitive pixels of the first pixel array into the IR light sensitive pixels of the second pixel array.
2. The apparatus of claim 1 further comprising a first vertical interconnect access that extends from a surface of said first semiconductor die that faces incident light to the second interconnect metallization of the second die.
3. The apparatus of claim 2 further comprising a second vertical interconnect access that extends from the surface of said first semiconductor die that faces incident light to the first interconnect metallization of the first die.
4. The apparatus of claim 3 wherein the first vertical interconnect access and the second vertical interconnect access are interconnected through third interconnect metallization that resides on the surface of the semiconductor die that faces incident light.
5. The apparatus of claim 4 further comprising a micro lens array formed on the third interconnect metallization.
6. The apparatus of claim 1 further comprising a micro lens array formed over a surface of the first semiconductor die that faces incident light.
7. The apparatus of claim 6 further comprising a vertical interconnect access that extends from the micro lens array to the second metallization of the second semiconductor die.