Memory system and information processing system

1. A memory system connectable to a host, comprising:

a nonvolatile memory;

a device controller configured to control the nonvolatile memory and to store a part of a logical-to-physical address translation table (L2P table) stored in the nonvolatile memory in a memory of the host as a cache; and

a tag memory including a plurality of entries, each of the plurality of entries being associated with each of a plurality of cache lines of the cache, each of the entries including a tag and a plurality of bitmap flags, the tag indicating which area of the L2P table is stored in a corresponding cache line, each of the plurality of bitmap flags corresponding to each of a plurality of sub-lines included in the corresponding cache line, each of the bitmap flags indicating whether a corresponding sub-line is valid or not, wherein

the device controller is configured to:

determine, by referring to the tag memory, whether a first cache line, which is associated with a tag including an upper bit portion of a first logical address designated by a command received from the host, is present in the cache or not, and whether a first bitmap flag, which is associated with a first sub-line in the first cache line, indicates validity or not, the first sub-line being a sub-line in which first physical address information corresponding to the first logical address is to be stored;

read, when the first cache line is present in the cache and the first bitmap flag indicates validity, the first physical address information from the first sub-line of the first cache line; and

invalidate, when the first cache line is absent in the cache and a non-used cache line is absent in the plurality of cache lines, a second cache line included in the cache, read the first physical address information from the L2P table of the nonvolatile memory, transfer the read first physical address information to a second sub-line of the second cache line to partly fill the second cache line, and update a bitmap flag associated with the second sub-line to a value indicative of validity, wherein the second sub-line is a sub-line in which the first physical address information is to be stored.

2. The memory system of claim 1 , wherein the device controller is configured to read, when the first cache line is present in the cache and the first bitmap flag indicates invalidity, the first physical address information from the L2P table of the nonvolatile memory, transfer the read first physical address information to the first sub-line of the first cache line to partly fill the first cache line, and update the first bitmap flag to a value indicative of validity.

3. The memory system of claim 1 , wherein the device controller is configured to update all bitmap flags corresponding to the second cache line to values indicative of invalidity to invalidate the second cache line.

4. The memory system of claim 1 , wherein the device controller is configured to read, when the first cache line is present in the cache and the first bitmap flag indicates invalidity, physical address information including a physical address corresponding to the first logical address and having a size corresponding to one sub-line, from the L2P table of the nonvolatile memory as the first physical address information.

5. The memory system of claim 1 , wherein each of the plurality of sub-lines has such a size as to be able to store a plurality of physical addresses corresponding to a plurality of consecutive logical addresses.

6. The memory system of claim 1 , wherein the device controller is configured to transfer, when the first cache line is present in the cache and the first bitmap flag indicates invalidity, only the first physical address information, which was read from the L2P table of the nonvolatile memory, to the first sub-line of the first cache line, and fill only the first sub-line of the first cache line with the first physical address information.

7. The memory system of claim 1 , wherein the device controller is configured to:

allocate a lower bit portion of a logical address, which is used by the host, as an in-sub-line index for specifying one of a plurality of physical addresses included in one sub-line; and

set a sub-line index for specifying one of the plurality of sub-lines between the lower bit portion of the logical address and an upper bit portion of the logical address to expand a line size of each of the plurality of cache lines to a size including the plurality of sub-lines.

8. The memory system of claim 7 , wherein the device controller is configured to:

determine a number of sub-lines which are included in each of the plurality of cache lines, based on a capacity of the cache placed on the memory of the host; and

set a bit portion for the sub-line index, which has a number of bits corresponding to the determined number of sub-lines, between the lower bit portion and the upper bit portion.

9. The memory system of claim 7 , wherein the cache is placed on a device use area allocated to the memory of the host, and

the device controller is configured to:

determine a capacity of the cache, based on a capacity of the device use area and a capacity of the nonvolatile memory;

determine a number of sub-lines which are to be included in each of the plurality of cache lines, based on the determined capacity of the cache; and

set a bit portion for the sub-line index, which has a number of bits corresponding to the determined number of sub-lines, between the lower bit portion and the upper bit portion.

10. An information processing system comprising a host and a memory system connectable to the host,

the host comprising:

a host controller connectable to the memory system; and

a memory, and

the memory system comprising:

a nonvolatile memory;

a device controller configured to control the nonvolatile memory and to store a part of a logical-to-physical address translation table (L2P table) stored in the nonvolatile memory in the memory of the host as a cache; and

a tag memory including a plurality of entries, each of the plurality of entries being associated with each of a plurality of cache lines of the cache, each of the entries including a tag and a plurality of bitmap flags, the tag indicating which area of the L2P table is stored in a corresponding cache line, each of the plurality of bitmap flags corresponding to each of a plurality of sub-lines included in the corresponding cache line, each of the bitmap flags indicating whether a corresponding sub-line is valid or not, wherein

the device controller is configured to:

determine, by referring to the tag memory, whether a first cache line, which is associated with a tag including an upper bit portion of a first logical address designated by a command received from the host, is present in the cache or not, and whether a first bitmap flag, which is associated with a first sub-line in the first cache line, indicates validity or not, wherein the first sub-line is a sub-line in which first physical address information corresponding to the first logical address is to be stored;

read, when the first cache line is present in the cache and the first bitmap flag indicates validity, the first physical address information from the first sub-line of the first cache line via the host controller, when the first cache line is present in the cache and the first bitmap flag indicates validity, and

invalidate, when the first cache line is absent in the cache and a non-used cache line is absent in the plurality of cache lines, a second cache line included in the cache, read the first physical address information from the L2P table of the nonvolatile memory, transfer, via the host controller, the first physical address information to a second sub-line of the second cache line to partly fill the second cache line, and update a bitmap flag associated with the second sub-line to a value indicative of validity, wherein the second sub-line is a sub-line in which the first physical address information is to be stored.

11. The information processing system of claim 10 , wherein the device controller is configured to read, when the first cache line is present in the cache and the first bitmap flag indicates invalidity, the first physical address information from the L2P table of the nonvolatile memory, transfer the read first physical address information to the first sub-line of the first cache line via the host controller to partly fill the first cache line, and update the first bitmap flag to a value indicative of validity.

12. The information processing system of claim 10 , wherein the device controller is configured to update all bitmap flags corresponding to the second cache line to values indicative of invalidity to invalidate the second cache line.

13. The information processing system of claim 10 , wherein the device controller is configured to read, when the first cache line is present in the cache and the first bitmap flag indicates invalidity, physical address information including a physical address corresponding to the first logical address and having a size corresponding to one sub-line, from the L2P table of the nonvolatile memory as the first physical address information.

14. The information processing system of claim 10 , wherein the device controller is configured to transfer, when the first cache line is present in the cache and the first bitmap flag indicates invalidity, only the first physical address information, which was read from the L2P table of the nonvolatile memory, to the first sub-line of the first cache line, and fill only the first sub-line of the first cache line with the first physical address information.

15. A method of controlling a memory system, the memory system connectable to a host including a memory, the memory system including a nonvolatile memory in which a logical-to-physical address translation table (L2P table) is stored, the method comprising:

storing a part of the L2P table in the memory of the host as a cache;

managing a tag memory, the tag memory including a plurality of entries, each of the plurality of entries being associated with each of a plurality of cache lines of the cache, each of the entries including a tag and a plurality of bitmap flags, the tag indicating which area of the L2P table is stored in a corresponding cache line, each of the plurality of bitmap flags corresponding to each of a plurality of sub-lines included in the corresponding cache line, each of the bitmap flags indicating whether a corresponding sub-line is valid or not;

determining, by referring to the tag memory, whether a first cache line, which is associated with a tag including an upper bit portion of a first logical address designated by a command received from the host, is present in the cache or not, and whether a first bitmap flag, which is associated with a first sub-line in the first cache line, indicates validity or not, the first sub-line being a sub-line in which first physical address information corresponding to the first logical address is to be stored;

reading, when the first cache line is present in the cache and the first bitmap flag indicates validity, the first physical address information from the first sub-line of the first cache line; and

invalidating, when the first cache line is absent in the cache and a non-used cache line is absent in the plurality of cache lines, a second cache line included in the cache, reading the first physical address information from the L2P table of the nonvolatile memory, transferring the read first physical address information to a second sub-line of the second cache line to partly fill the second cache line, and updating a bitmap flag associated with the second sub-line to a value indicative of validity, the second sub-line being a sub-line in which the first physical address information is to be stored.

16. The method of claim 15 , further comprising

reading, when the first cache line is present in the cache and the first bitmap flag indicates invalidity, the first physical address information from the L2P table of the nonvolatile memory, transferring the read first physical address information to the first sub-line of the first cache line to partly fill the first cache line, and updating the first bitmap flag to a value indicative of validity.

17. The method of claim 15 , further comprising

updating all bitmap flags corresponding to the second cache line to values indicative of invalidity to invalidate the second cache line.

18. The method of claim 15 , further comprising

reading, when the first cache line is present in the cache and the first bitmap flag indicates invalidity, physical address information including a physical address corresponding to the first logical address and having a size corresponding to one sub-line, from the L2P table of the nonvolatile memory as the first physical address information.

19. The method of claim 15 , wherein each of the plurality of sub-lines has such a size as to be able to store a plurality of physical addresses corresponding to a plurality of consecutive logical addresses.

20. The method of claim 15 , further comprising:

transferring, when the first cache line is present in the cache and the first bitmap flag indicates invalidity, only the first physical address information, which was read from the L2P table of the nonvolatile memory, to the first sub-line of the first cache line; and

filling only the first sub-line of the first cache line with the first physical address information.