Data processor selecting a flag out of a plurality of flags generated by an instruction operating on multiple operand sizes in parallel
View Patent ↗The RISC data processor is based on the idea that in case that there are many flag-generating instructions, the number of flags generated by each instruction is increased so that a decrease of flag-generating instructions exceeds an increase of flag-using instructions in quantity, thereby achieving the decrease in instructions. With the data processor, an instruction for generating flags according to operands' data sizes is defined. To an instruction set handled by the RISC data processor, an instruction capable of executing an operation on operand in more than one data size, which performs a process identical to an operation process conducted on the small-size operand on low-order bits of the large-size operand, and generates flags capable of coping with the respective data sizes regardless of the data size of each operand subjected to the operation is added. Thus, the reduction in instruction code space of the RISC data processor tight in instruction code space can be achieved.
1. A data processor of Reduced Instruction Set Computer type, comprising an instruction-execution unit configured to execute instructions of an instruction set,
wherein the instructions include a first instruction which causes the instruction-execution unit to execute a process involving flag generation, and a second instruction which causes the instruction-execution unit to execute a process involving use of a flag,
wherein the instruction-execution unit comprises:
an operation circuit operable to perform a process according to a result of a decode of an instruction;
a first flag select circuit;
a second flag select circuit;
a first flag latch circuit;
a second flag latch circuit; and
a third flag select circuit,
wherein the operation circuit, which is capable of performing on operands in more than one data size according to a result of a decode of the first instruction, is configured to perform an identical process on low-order bits of a large data size operand and on a small data size operand, and generate a first flag group corresponding to the large data size operand and a second flag group corresponding to the small data size operand,
wherein the first flag select circuit is configured to select a first flag out of the first flag group according to a result of the decode of the first instruction,
wherein the second flag select circuit is configured to select a second flag out of the second flag group according to a result of the decode of the first instruction,
wherein the first flag latch circuit is configured to latch the first flag,
wherein the second flag latch circuit is configured to latch the second flag,
wherein the third flag select circuit is configured to select one among the first flag latched by the first flag latch circuit and the second flag latched by the second flag latch circuit.
2. The data processor according to claim 1 ,
wherein the instruction set has a prefix instruction which modifies a subsequent instruction, and
wherein the modification includes designating a flag among the first flag and the second flag to be updated by a flag generated by the subsequent instruction.
3. The data processor according to claim 1 ,
wherein the instruction set has a prefix instruction which modifies a subsequent instruction,
wherein the modification includes:
designating a flag among the first flag and the second flag to be updated by a flag generated by the subsequent instruction,
designating another flag among flags generated by the subsequent instruction to be used, and
designating a logical operation between the two designated flags.
4. The data processor according to claim 1 ,
wherein the small data size is 32 bits and the large data size is 64 bits.
5. The data processor according to claim 1 ,
wherein the first and second flag groups include flags of Signed Large and Signed Small, Unsigned Large and Unsigned Small, Zero, Overflow, Carry and Shift-out bit for each data size.