Methods for combining instructions and apparatuses having multiple data pipes

1. A method for combining instructions, performed by a compiler, the method comprising:

obtaining a plurality of first instructions, wherein each first instruction performs one of a calculation operation, a comparison operation, a logic operation, a selection operation, a branching operation, a LD/ST (Load/Store) operation, a SMP (sampling) operation and a complicated mathematics operation;

combining the first instructions according to data dependencies between the first instructions;

obtaining a second instruction, wherein the second instruction is used for sending data from a CR (Common Register) or a CB (Constant Buffer) to another CR or a post-processing unit;

combining a combined result for the first instructions with the second instruction as one combined instruction; and

sending the combined instruction to a SP (Stream Processor),

wherein a performance of an operation of the first instructions by the SP is in parallel of a performance of an operation of the second instruction by the SP, wherein the SP comprises:

a DF (Data Fetch) unit;

a bypass-pipe, coupled to a CR (Common Register), a CB (Constant Buffer) and the DF unit; and

a main-pipe, coupled to the DF unit and the bypass-pipe, comprising an ALG (Algorithm) unit, a comparison/logic unit and a post-PROC (Process) unit,

wherein the ALG, comparison/logic and post-PROC units are coupled in series and each of the ALG, comparison/logic and post-PROC units is coupled to the bypass-pipe, and

wherein a first computation unit of the ALG unit is coupled to the bypass-pipe and the DF unit for obtaining operands from the bypass-pipe and/or the DF unit.

2. The method of claim 1 , wherein the first instructions are combined according to the following rules:

ALG+CMP+SEL;

ALG+CMP+SEL+SFU/LS/SMP;

ALG+CMP+Branch;

ALG+LGC+SEL;

ALG+LGC+SEL+SFU/LS/SMP; or

ALG+LGC+Branch,

ALG indicates a calculation instruction, CMP indicates a comparison instruction, LGC indicates a logic instruction, SEL indicates a selection instruction, Branch indicates a branching instruction, SFU indicates a mathematics computation instruction, LS indicates a Load/Store instruction and SMP indicates a sampling instruction.

3. The method of claim 1 , wherein a second computation unit of the comparison/logic unit is coupled to the bypass-pipe and a first output of the first computation unit for obtaining operands from the bypass-pipe and/or the first output; and a third computation unit of the post-PROC unit is coupled to the bypass-pipe, the first output of the first computation unit and a second output of the second computation unit for obtaining operands from the bypass-pipe, the first output and/or the second output.

4. The method of claim 1 , wherein the main-pipe executes the first instructions and the bypass-pipe executes the second instruction.

5. An apparatus having a plurality of data pipes, comprising:

logic for obtaining a plurality of first instructions, wherein each first instruction performs one of a calculation operation, a comparison operation, a logic operation, a selection operation, a branching operation, a LD/ST (Load/Store) operation, a SMP (sampling) operation and a complicated mathematics operation;

logic for combining the first instructions according to data dependencies between the first instructions;

logic obtaining a second instruction, wherein the second instruction is used for sending data from a CR (Common Register) or a CB (Constant Buffer) to another CR or a post-processing unit;

logic for combining a combined result for the first instructions with the second instruction as one combined instruction; and

logic for sending the combined instruction to a SP (Stream Processor),

wherein a performance of an operation of the first instructions by the SP is in parallel of a performance of an operation of the second instruction by the SP, wherein the SP comprises:

a DF (Data Fetch) unit;

a bypass-pipe, coupled to a CR (Common Register), a CB (Constant Buffer) and the DF unit; and

a main-pipe, coupled to the DF unit and the bypass-pipe, comprising an ALG (Algorithm) unit, a comparison/logic unit and a post-PROC (Process) unit,

wherein the ALG, comparison/logic and post-PROC units are coupled in series and each of the ALG, comparison/logic and post-PROC units is coupled to the bypass-pipe,

wherein the main-pipe performs an operation of a main-pipe instruction and the bypass-pipe performs an operation of a bypass-pipe instruction in parallel, and

wherein a first computation unit of the ALG unit is coupled to the bypass-pipe and the DF unit for obtaining operands from the bypass-pipe and/or the DF unit.

6. The apparatus of claim 5 , wherein a first computation unit of the ALG unit is coupled to the bypass-pipe and the DF unit for obtaining operands from the bypass-pipe and/or the DF unit; a second computation unit of the comparison/logic unit is coupled to the bypass-pipe and a first output of the first computation unit for obtaining operands from the bypass-pipe and/or the first output; and a third computation unit of the post-PROC unit is coupled to the bypass-pipe, the first output of the first computation unit and a second output of the second computation unit for obtaining operands from the bypass-pipe, the first output and/or the second output.

7. The apparatus of claim 6 , wherein the third computation unit is coupled to a LD/ST (Load/Store) unit, a SMP (Sampling) unit and a SFU (Special Function Unit) for outputting an operation result.

8. The apparatus of claim 7 , wherein the LD/ST unit performs a loading or storing instruction, the SMP unit performs a texture sampling instruction and the SFU unit performs a mathematics computation instruction.

9. The apparatus of claim 5 , wherein the main-pipe instruction is one of a calculation instruction, a comparison instruction, a logic instruction, a selection instruction and a branching instruction and the bypass-pipe instruction is a moving instruction.