System and method for dynamic optimization for burst and sustained performance in solid state drives
A method and information handling system configured to executing instructions of an SSD dynamic optimization buffer switching system and configured to detecting SSD storage capacity utilization via an SSD controller. The method and information handling system further configured to reallocate buffer capacity from write acceleration buffer capacity to garbage collection buffer capacity to increase buffer availability for garbage collection when SSD storage capacity utilization exceeds a threshold level.
1. An information handling system comprising:
a solid state drive (SSD) memory device;
an SSD controller executing instructions of an SSD dynamic optimization buffer switching system;
the SSD controller detecting SSD storage capacity utilization; and
the SSD controller reallocating buffer capacity from write acceleration buffer capacity to garbage collection buffer capacity to increase buffer availability for garbage collection when SSD storage capacity utilization exceeds a threshold level.
2. The information handling system of claim 1 wherein reallocating buffer capacity switches from a single level cell (SLC) NAND buffer for write acceleration to a triple-level cell (TLC) NAND buffer for additional garbage collection buffer capacity.
3. The information handling system of claim 1 wherein the SSD storage capacity utilization threshold level is a used block count set at a level of 65% or greater of a total available block count for the SSD memory device.
4. The information handling system of claim 1 further comprising:
the SSD controller increasing a count for an incremental buffer switch counter for each buffer capacity reallocation.
5. The information handling system of claim 4 further comprising:
the SSD controller determining that the count of the incremental buffer switch counter is below a reliability buffer switching threshold count; and
the SSD controller proceeding to switch from a single level cell (SLC) NAND buffer capacity for write acceleration to a triple-level cell (TLC) NAND buffer capacity for additional garbage collection buffer capacity.
6. The information handling system of claim 4 further comprising:
the SSD controller determining that the count of the incremental buffer switch counter is below the buffer switching threshold count; and
the SSD controller cancelling buffer capacity reallocation.
7. The information handling system of claim 1 further comprising:
the SSD controller running a garbage collection algorithm to return freed blocks to a freed block list.
8. The information handling system of claim 7 further comprising:
the SSD controller detecting SSD storage capacity utilization after garbage collection; and
the SSD controller reallocating buffer capacity from garbage collection buffer capacity to write acceleration buffer capacity to increase buffer availability for write acceleration when SSD storage capacity utilization falls below a second SSD storage capacity utilization threshold level.
9. A computerized method of solid state drive (SSD) dynamic optimization comprising:
executing instructions, via an SSD controller, of an SSD dynamic optimization buffer switching system;
detecting SSD storage capacity utilization via the SSD controller; and
reallocating buffer capacity from write acceleration buffer capacity to garbage collection buffer capacity to increase buffer availability for garbage collection when SSD storage capacity utilization exceeds a threshold level.
10. The computerized method of claim 9 wherein reallocating buffer capacity switches from a single level cell (SLC) NAND buffer for write acceleration to a triple-level cell (TLC) NAND buffer for additional garbage collection buffer capacity.
11. The computerized method of claim 9 wherein the SSD storage capacity utilization threshold level is a used block count of 90%+/−5% of a total available block count for the SSD memory device.
12. The computerized method of claim 9 further comprising:
increasing a count for an incremental buffer switch counter for each buffer capacity reallocation.
13. The computerized method of claim 12 further comprising:
determining, via the SSD controller, that the count of the incremental buffer switch counter is below a reliability buffer switching threshold count; and
permitting a switch from a single level cell (SLC) NAND buffer capacity for write acceleration to a triple-level cell (TLC) NAND buffer capacity for additional garbage collection buffer capacity.
14. The computerized method of claim 12 further comprising:
determining, via the SSD controller, that the count of the incremental buffer switch counter is below the buffer switching threshold count; and
cancelling buffer capacity reallocation.
15. The information handling system of claim 9 further comprising:
detecting SSD storage capacity utilization after a garbage collection algorithm is executed; and
reallocating buffer capacity from garbage collection buffer capacity to write acceleration buffer capacity to increase buffer availability for write acceleration when SSD storage capacity utilization falls below a second SSD storage capacity utilization threshold level.
16. The computerized method of claim 15 wherein the second SSD storage capacity utilization threshold level is a used block count of 75%+/−5% of an IDEMA logical block addressing count.
17. An information handling system comprising:
a solid state drive (SSD) memory device;
an SSD controller executing instructions of an SSD dynamic optimization buffer switching system;
the SSD controller running a garbage collection algorithm to return freed SSD storage blocks to a freed block list;
the SSD controller detecting SSD storage capacity utilization; and
the SSD controller reallocating reallocates a portion of a buffer capacity from write acceleration buffer capacity to a garbage collection buffer capacity to increase buffer availability for garbage collection when SSD storage capacity utilization exceeds a threshold level.
18. The information handling system of claim 17 further comprising:
the SSD dynamic optimization buffer switching system halting write acceleration when all write acceleration buffer capacity has been reallocated to the garbage collection buffer.
19. The information handling system of claim 17 wherein reallocating buffer capacity switches from a single level cell (SLC) NAND buffer for write acceleration to a triple-level cell (TLC) NAND buffer for additional garbage collection buffer capacity.
20. The information handling system of claim 17 wherein the SSD controller reallocates a portion of the buffer capacity from write acceleration buffer capacity to the garbage collection buffer capacity to increase buffer availability for garbage collection when SSD storage capacity utilization exceeds a threshold level.