Semiconductor device

1. A semiconductor device comprising:

an input terminal which receives a first clock;

an output terminal;

an oscillation circuit which generates an internal clock;

an adjuster circuit which corrects a duty ratio of a clock;

a driver circuit which receives the clock from the adjuster circuit and supplies a third clock to the output terminal;

a detector circuit which detects that a duty ratio of a clock according to the third clock deviates from a duty ratio of a second clock according to the internal clock; and

a selection circuit connected between the input terminal and the adjuster circuit,

wherein the adjuster circuit adjusts a correction amount in tune with the second clock, and corrects a duty ratio of the first clock with the adjusted correction amount according to a detection result of the detector circuit, and

the selection circuit includes a first input node connected to the input terminal, a second input node which receives the second clock, and an output node connected to the adjuster circuit.

2. The semiconductor device according to claim 1 , wherein

the selection circuit selects either a signal received in the first input node or a signal received in the second input node, and supplies the selected signal to the adjuster circuit.

3. The semiconductor device according to claim 1 , wherein

the selection circuit selects either the first clock or the second clock, and supplies the selected clock to the adjuster circuit.

4. The semiconductor device according to claim 1 , wherein

the selection circuit further selects the second clock to supply the selected second clock to the adjuster circuit in a first period, and selects the first clock to supply the selected first clock to the adjuster circuit in a second period following the first period, and

the adjuster circuit adjusts the correction amount using the second clock in the first period, and corrects the duty ratio of the first clock with the adjusted correction amount in the second period.

5. The semiconductor device according to claim 4 , wherein

the first period includes a period from when the semiconductor device starts up to when the first clock is supplied to the input terminal.

6. The semiconductor device according to claim 1 , wherein

the detector circuit receives the clock according to the third clock, and detects that a duty ratio of the third clock deviates from the duty ratio of the second clock.

7. The semiconductor device according to claim 1 , further comprising:

a replica circuit which has a characteristic equivalent to the driver circuit, receives the clock from the adjuster circuit, and outputs a fourth clock.

8. The semiconductor device according to claim 7 , wherein

the detector circuit receives the fourth clock, and detects that a duty ratio of the fourth clock deviates from the duty ratio of the second clock.

9. The semiconductor device according to claim 8 , wherein:

the selection circuit selects the second clock and supplies the second clock to the adjuster circuit in a first period, and selects the first clock and supplies the first clock to the adjuster circuit in a second period following the first period,

the detector circuit detects that the duty ratio of the fourth clock deviates from the duty ratio of the second clock in the first period, and detects that the duty ratio of the fourth clock deviates from the duty ratio of the first clock in the second period, and

the adjuster circuit adjusts a correction amount according to a detection result of the detector circuit in the first period, and corrects the first clock while further adjusting the adjusted correction amount according to the detection result of the detector circuit in the second period.

10. The semiconductor device according to claim 8 , wherein

the internal clock has a frequency of m times the first clock, where m is an integer of 2 or more,

the second clock is generated by frequency-dividing the internal clock by m,

the semiconductor device further comprises:

the selection circuit which selects the second clock and supplies the second clock to the adjuster circuit in a first period, and selects the first clock and supplies the first clock to the adjuster circuit in a second period following the first period,

the detector circuit detects that the duty ratio of the fourth clock deviates from the duty ratio of the second clock in the first period and in the second period, and

the adjuster circuit adjusts the correction amount according to a detection result of the detector circuit in the first period, and corrects the first clock while further adjusting the adjusted correction amount according to the detection result of the detector circuit in the second period.

11. The semiconductor device according to claim 1 , wherein

the adjuster circuit includes

a first RC circuit which adjusts timing of a rising edge of a clock selected by the selection circuit, and

a second RC circuit which adjusts timing of a falling edge of the selected clock.

12. The semiconductor device according to claim 11 , wherein

the second RC circuit includes

an input inverter which includes a PMOS transistor and an NMOS transistor and receives an inverted clock,

an output inverter which outputs a clock according to a signal transmitted from the input inverter through a signal line,

a variable capacitance element connectable to the signal line, and

a resistance element connected to a source of the NMOS transistor.

13. A semiconductor device comprising:

an input terminal which receives a first clock;

an output terminal;

an oscillation circuit which generates an internal clock;

an adjuster circuit which corrects a duty ratio of a clock;

a driver circuit which receives the clock from the adjuster circuit and supplies a third clock to the output terminal; and

a detector circuit which detects that a duty ratio of a clock according to the third clock deviates from a duty ratio of a second clock according to the internal clock,

wherein the adjuster circuit adjusts a correction amount in tune with the second clock, and corrects a duty ratio of the first clock with the adjusted correction amount according to a detection result of the detector circuit,

the internal clock has a frequency of m times the first clock, where m is an integer of 2 or more, and

the second clock is generated by frequency-dividing the internal clock by m.

14. The semiconductor device according to claim 13 , wherein

the detector circuit receives the clock according to the third clock, and detects that a duty ratio of the third clock deviates from the duty ratio of the second clock.

15. The semiconductor device according to claim 13 , further comprising:

a replica circuit which has a characteristic equivalent to the driver circuit, receives the clock from the adjuster circuit, and outputs a fourth clock.

16. The semiconductor device according to claim 13 , wherein

the adjuster circuit includes

a first RC circuit which adjusts timing of a rising edge of the first clock, and a second RC circuit which adjusts timing of a falling edge of the first clock.

17. A semiconductor device comprising:

a first voltage conversion circuit which converts a duty ratio of a first clock into a voltage;

a second voltage conversion circuit which converts a duty ratio of a second clock into a voltage; and

a comparator which compares the voltage of the first voltage conversion circuit and the voltage of the second voltage conversion circuit,

wherein deviation of the duty ratio of the first clock from the duty ratio of the second clock is detected according to a comparison result of the comparator,

the first voltage conversion circuit includes a first capacitance element, and

the second voltage conversion circuit includes a second capacitance element, and

the semiconductor device further comprising

a charge/discharge circuit which charges the first capacitance element during a period in which the first clock is in a first level, discharges the first capacitance element during a period in which the first clock is in a second level, charges the second capacitance element during a period in which the second clock is in the first level, and discharges the second capacitance element during a period in which the second clock is in the second level.

18. The semiconductor device according to claim 17 , wherein

the charge/discharge circuit includes

a PMOS transistor having a drain connected to a node,

an NMOS transistor having a drain connected to the node,

a first current source connected between the PMOS transistor and a power supply potential,

a second current source connected between the NMOS transistor and a ground potential,

a first switch which allows the node connected to be connected to one end of the first capacitance element, and

a second switch which allows the node to be connected to one end of the second capacitance element.

19. The semiconductor device according to claim 18 , further comprising:

a selector which receives the first clock and the second clock, wherein

a signal according to a clock selected in the selector is supplied to gates of the PMOS transistor and the NMOS transistor.

20. The semiconductor device according to claim 19 , wherein

the first switch connects the charge/discharge circuit to the first capacitance element when the selector has selected the first clock, and

the second switch connects the charge/discharge circuit to the second capacitance element when the selector has selected the second clock.