Semiconductor memory device and operating method thereof

1. A method for operating a semiconductor memory device including at least two memory blocks sharing one block word line, the method comprising:

applying an erase voltage to a source line commonly coupled to the memory blocks, one of which is a selected memory block; and

applying a first voltage to the block word line and a third voltage to a global word line of an unselected memory block of the memory blocks when the erase voltage is applied to the source line,

wherein the first voltage is higher than a turn-on voltage to turn on a pass transistor coupled to the block word line, and

wherein the third voltage floats a local word line included in the unselected memory block according to a level of the first voltage.

2. The method of claim 1 , further comprising applying a second voltage lower than the first voltage to the block word line and a fourth voltage to the global word line to float the local word line included in the unselected memory block according to the second voltage when a predetermined time passes.

3. The method of claim 2 , wherein the second voltage has a level to turn on the pass transistor coupled to the block word line.

4. The method of claim 2 , wherein the first voltage is higher than the second voltage by a predetermined voltage level.

5. The method of claim 2 , wherein the fourth voltage is lower than the third voltage.

6. The method of claim 4 , wherein the fourth voltage is lower than the third voltage by the predetermined voltage level.

7. The method of claim 1 , further comprising applying the third voltage to a source selection line and a drain selection line of the unselected memory block while applying the third voltage the global word line of the unselected memory block.

8. A semiconductor memory device, comprising:

at least two memory blocks sharing one block word line;

a peripheral circuit suitable for performing an erase operation on a selected memory block of the memory blocks; and

a control circuit suitable for controlling the peripheral circuit to apply a first voltage to the block word line and a third voltage to a global word line of an unselected memory block of the memory blocks when an erase voltage is applied to a source line commonly coupled to the memory blocks,

wherein the first voltage is higher than a turn-on voltage to turn on a pass transistor coupled to the block word line, and

wherein the third voltage floats a local word line included in the unselected memory block according to a level of the first voltage.

9. The semiconductor memory device of claim 8 , wherein the control circuit further controls the peripheral circuit to apply a second voltage lower than the first voltage to the block word line and a fourth voltage to the global word line to float the local word line included in the unselected memory block according to the second voltage when a predetermined time passes.

10. The semiconductor memory device of claim 9 , wherein the second voltage has a level to turn on the pass transistor coupled to the block word line.

11. The semiconductor memory device of claim 9 , wherein the first voltage is higher than the second voltage by a predetermined voltage level.

12. The semiconductor memory device of claim 9 , wherein the fourth voltage is lower than the third voltage.

13. The semiconductor memory device of claim 11 , wherein the fourth voltage is lower than the third voltage by the predetermined voltage level.

14. The semiconductor memory device of claim 8 , wherein the control circuit further controls the peripheral circuit to apply the third voltage to a source selection line and a drain selection line of the unselected memory block while applying the third voltage to the global word line of the unselected memory block.

15. A semiconductor memory device, comprising:

an address decoder including a plurality of block decoders; and

at least two memory blocks, one of which is a selected memory block, corresponding to one of the block decoders,

wherein the address decoder applies a first voltage to a block word line, which is an output line of the block decoder, and a third voltage to a global word line of an unselected memory block of the memory blocks when an erase voltage is applied to a source line coupled commonly to the memory blocks,

wherein the first voltage is higher than a turn-on voltage which turns on a pass transistor coupled to the block word line, and

wherein the third voltage floats a local word line included in the unselected memory block according to a level of the first voltage.

16. The semiconductor memory device of claim 15 , wherein the address decoder comprises:

a block decoder unit suitable for outputting block selection signals in response to an address; and

a pass unit suitable for respectively coupling global word lines to local word lines of the memory blocks.

17. The semiconductor memory device of claim 15 , wherein the address decoder further applies a second voltage lower than the first voltage to the block word line and a fourth voltage to the global word line to float the local word line included in the unselected memory block according to the second voltage.

18. The semiconductor memory device of claim 17 , wherein the second voltage has a level to turn on the pass transistor coupled to the block word line.

19. The semiconductor memory device of claim 17 , wherein the first voltage is higher than the second voltage by a predetermined voltage level.

20. The semiconductor memory device of claim 19 , wherein the fourth voltage is lower than the third voltage by the predetermined voltage level.