Microdisplay pixel cell and method of making it
View Patent ↗A plurality of active areas are defined on a semiconductor substrate. Then at least one gate is formed on the semiconductor substrate to cover a portion of the active area. Thereafter a plurality of source/drain are formed in the active area not covered by the gate followed by forming a first dielectric layer on the semiconductor substrate to cover the gate and the source/drain. After that, at least one pixel cap top plate is formed atop the first dielectric layer and a capacitor dielectric layer is formed atop the surface of the top plate. Finally, at least one pixel cap bottom plate is formed atop the first dielectric layer to cover the top plate.
1. A microdisplay pixel cell device, the device comprising:
a semiconductor substrate defined with a plurality of active areas;
two gates, each of the gates covering a portion of the active areas;
four sources and two drains, the sources and the drains being in the active areas not covered by the gates;
a first dielectric layer, the first dielectric layer covering the two gates, the four sources and the four drains, the first dielectric layer comprising at least one row select contact plug to electrically connect to the one of the gates;
at least one row select line, the row select line being atop the first dielectric layer, the row select line being electrically connected to one of the gates through the row select contact plug;
a second dielectric layer, the second dielectric layer being atop the first dielectric layer and covering the row select line;
four pixel cap top plates, each of the pixel cap top plates being atop the second dielectric layer and partially covering one of the active areas and one of the gates, and being electrically connected to one of the sources;
at least one first contact plug, the first contact plug being in the first dielectric layer and the second dielectric layer for electrically connecting one of the sources and one of the top plates;
at least one capacitor dielectric layer, the capacitor dielectric layer being atop the surfaces of the top plates; and
one pixel cap bottom plate, the pixel cap bottom plate being atop the second dielectric layer and covering all of the two gates, the four sources, the two drains, the four top plates and the capacitor dielectric layer.
2. The device of claim 1 wherein each of the gates comprises a gate oxide layer, a polysilicon layer or a metal silicide layer.
3. The device of claim 1 wherein at least one second contact plug is comprised in the first dielectric layer and the second dielectric layer for electrically connecting one of the drains to a video data line.
4. The device of claim 1 wherein the row select line is composed of a metal and is used as a scan line of the microdisplay.
5. The device of claim 1 wherein the bottom plate and the top plates are composed of a metal.
6. The device of claim 5 wherein the bottom plate and the top plates are composed of titanium (Ti), titanium nitride (TiN), aluminum (Al), copper (Cu) or an alloy of above-mentioned materials.
7. The device of claim 1 wherein the microdisplay is a reflective liquid crystal on silicon (LCOS) display.
8. A microdisplay pixel cell device, the device comprising:
a semiconductor substrate;
a transistor block formed on the semiconductor substrate, the transistor block comprising a plurality of transistors comprising a plurality of sources;
a first dielectric layer covering the transistors, the first dielectric layer comprising at least one row select contact plug to electrically connect to a gate of the transistors;
at least one row select line formed atop the first dielectric layer, the row select line being electrically connected to the gate through the row select contact plug;
a second dielectric layer formed atop the first dielectric layer to cover the row select line;
a plurality of pixel cap top plates formed atop the transistors and positioned on the second dielectric layer, each of the pixel cap top plates being electrically connected to one of the sources;
at least one capacitor dielectric layer formed atop the top plates; and
one pixel cap bottom plate formed atop the second dielectric layer to cover the whole transistor block, the capacitor dielectric layer and all of the plurality of pixel cap top plates.
9. The device of claim 8 wherein at least one first contact plug is comprised in the first dielectric layer and the second dielectric layer for electrically connecting one of the sources of the transistors and one of the top plates.
10. The device of claim 8 wherein at least one second contact plug is comprised in the first dielectric layer and the second dielectric layer for electrically connecting a drain of the transistors to a video data line.
11. The device of claim 8 wherein the row select line is composed of a metal and is used as a scan line of the microdisplay.
12. The device of claim 8 wherein the bottom plate and the top plates are composed of a metal.
13. The device of claim 8 wherein the bottom plate and the top plates are composed of titanium (Ti), titanium nitride (TiN), aluminum (Al), copper (Cu) or an alloy of above-mentioned materials.
14. The device of claim 8 wherein the transistor block comprises two gates, two common drains, and four sources to define four transistors.
15. The device of claim 14 wherein the microdisplay pixel cell device comprises four top plates to cover the four transistors in the transistor block, respectively.
16. The device of claim 8 wherein the microdisplay is a reflective liquid crystal on silicon (LCOS) display.