Current inrush limiting circuit
View Patent ↗An inrush circuit for electronic devices is particularly useful for point-of-sale printers. The circuit applies an active feedback-controlled voltage ramp to a bulk capacitor by means of a P-channel field effect transistor that is operated linearly after a controlled delay for contact bounce.
1. An inrush circuit for electronic devices having high input capacitance, said inrush circuit comprising:
a. means for providing a voltage ramp;
b. means defining an output voltage;
c. an operational amplifier circuit having a reference input, said operational amplifier circuit receiving said voltage ramp at said reference input and comparing a divided sample of said output voltage with the voltage ramp, said operational amplifier operating in a linear mode, whereby said output voltage approximates a multiple of the voltage ramp;
d. transistor means electronically connected to said operational amplifier circuit, said transistor means operating in linear mode during capacitor charging, and subsequently reaching a full-ON state; and
e. energy storage load means connected to said transistor means for receiving a full power supply after said transistor means reaches its said full-ON state.
2. The inrush circuit for electronic devices in accordance with claim 1 , wherein said transistor means comprises a power field effect transistor.
3. The inrush circuit for electronic devices in accordance with claim 1 , wherein said output voltage approximates the voltage ramp by a gain of two.
4. The inrush circuit for electronic devices in accordance with claim 1 , wherein said electronic devices comprise a point-of-sale printer.
5. The inrush circuit for electronic devices in accordance with claim 2 , wherein said field effect transistor is operative initially in an OFF state, and subsequently becomes operative in a full-ON state.
6. The inrush circuit for electronic devices in accordance with claim 5 , wherein said field effect transistor is part of a linear feedback loop, and further comprising capacitive means electronically connected to said field effect transistor for ensuring that said field effect transistor is initially operative in said OFF state, said capacitive means being minimized to subsequently prevent interfering with said linear feedback loop.
7. The inrush circuit for electronic devices in accordance with claim 2 , further comprising capacitive means electronically connected to said operational amplifier for preventing oscillation thereof.
8. The inrush circuit of claim 1 , further comprising time delay means connected to said means for providing a voltage ramp.
9. The inrush circuit of claim 8 , wherein said time delay means reaches threshold in about 50 ms.
10. The inrush circuit of claim 1 , wherein said energy storage load means is a bulk capacitor.