Semiconductor integrated circuit device comprising RAM with command decode system and logic circuit integrated into a single chip and testing method of the RAM with command decode system

1. A semiconductor integrated circuit device comprising:

a logic circuit and ;

a synchronous dynamic random access memory including a core unit, said logic circuit and said synchronous dynamic random access memory being integrated into a single semiconductor chip; and

a synchronous dynamic random access memory control circuit receiving external control signals for said synchronous dynamic random access memory from said logic circuit, and outputting internal control signals to said core unit of said synchronous dynamic random access memory, wherein the output signals from said synchronous dynamic random access memory control circuit are internal control signals for controlling control said core unit of said synchronous dynamic random access memory.

2. The semiconductor integrated circuit device according to claim 1 further comprising:

external input terminal means for transmitting a first group of internal control signals for said synchronous dynamic random access memory; and

select means for supplying internal control signals to said core unit of said synchronous dynamic random access memory, said the internal control signals being obtained by selecting either the first group of internal control signals received from said synchronous dynamic random access memory control circuit, wherein said select means has a first mode selecting the first group of internal control signals received from said external input terminals for testing said semiconductor integrated circuit device with the first group of signals, and second mode selecting the second group of internal control signals received from said synchronous dynamic random access memory control circuit.

3. The semiconductor integrated circuit device according to claim 1 further comprising:

external input terminal means for transmitting internal control signals for said synchronous dynamic random access memory;

synchronizing means for receiving the internal control signals from said external input terminal means and outputting a first group of internal control signals synchronized with a clock signal of said semiconductor integrated circuit; and

select means for supplying internal control signals to said core unit of said synchronous dynamic random access memory, said the internal control signals being obtained by selecting either the first group of internal control signals received from said synchronizing means or a second group of internal control signals received from said synchronous dynamic random access memory control circuit, wherein said select means has a first mode selecting the first group of internal control signals received from said synchronizing means, and a second mode selecting the group of internal control signals received from said synchronous dynamic random access memory control circuit.

4. The semiconductor integrated circuit device according to claim 1 further ocmprisign:

external input terminal means for transmitting external control signals for said synchronous dynamic random access memory;

a command decoder for decoding the external control signals received from said external input terminal means into a first group of internal control signals for controlling said core unit of said synchronous dynamic random access memory; and

select means for supplying internal control signals to said core unit of said synchronous dynamic random access memory, the internal control signals being obtained by selecting either the first group of internal control signals received from said command decoder or a second group of internal control signals received from said synchronous dynamic random access memory control circuit, wherein said select means has a first mode selecting the first group of internal control signals received from said command decoder, and a second mode for selecting the second group of internal control signals received from said synchronous dynamic random access memory control circuit.

5. A The semiconductor integrated circuit device according to claim 1 further comprising:

external input terminal means for transmitting external control signals for said synchronous dynamic random access memory;

synchronizing means for receiving the external control signals from said external input terminal means and outputting external control signals synchronized with a clock signal of said semiconductor integrated circuit; and

a command decoder for decoding the external control signals received from said synchronizing means into a first group of internal control signals for controlling said core unit of said synchronous dynamic random access memory; and

select means for supplying internal control signals to said core unit of said synchronous dynamic random access memory, the internal control signals being obtained by selecting either the first group of internal control signals received from said command decoder or a second group of internal control signals received from said synchronous dynamic random access memory control circuit, wherein said select means has a first mode selecting the first group of internal control signals received from said command decoder and a second mode selecting the second group of internal control signals received from said synchronous dynamic random access memory control circuit.

6. The semiconductor integrated circuit device according to claim 1 further comprising:

external input terminal means for transmitting external control signals for said synchronous dynamic random access memory;

a command decoder for decoding the external control signals received from said external input terminal means into internal control signals for controlling said core unit of said synchronous dynamic internal control signal random access memory;

a synchronizing means receiving the internal control signals from said command decoder for outputting a first group of internal control signals synchronized with a clock signal of said semiconductor integrated circuit; and

select means for supplying the internal control signals to said core unit of said synchronous dynamic random access memory, the internal control signals being obtained by selecting either the first group of internal control signals received from said synchronizing means or a second group of internal control signals received from said synchronous dynamic random access memory control circuit, wherein said select means has a first mode selecting the first group of internal control signals received from said synchronizing means and a second mode selecting the second group of internal control signals received from said synchronous dynamic random access memory control circuit.

7. A method for testing a semiconductor integrated circuit device, said test method including the steps of comprising: , in a logic circuit and a synchronous dynamic random access memory including a core unit, said logic circuit and said synchronous dynamic random access memory being integrated into a single semiconductor chip; and ;

providing external test signals through external input terminal means to a selector;

providing internal control signals from a synchronous dynamic random access memory control circuit to a the selector; and

selecting said the external test signals from said the external input terminal means, using said the selector, for and providing the selected signals to a core unit of said synchronous dynamic random access memory for testing, wherein the external test signals are external control signals for said core unit of said synchronous dynamic random access memory, and are decoded by a decoder to be the internal control signals provided to said selector.

8. The method for testing a semiconductor integrated circuit device according to claim 7 , wherein the external test signals are internal control signals for testing said core unit of said synchronous dynamic random access memory.

9. The method for testing a semiconductor integrated circuit device according to claim 7 , wherein the external test signals are external control signals for said core unit of said synchronous dynamic random access memory, and is are decoded by a decoder to be the internal control signals provided to said selector.

10. A semiconductor integrated circuit device comprising:

a logic circuit;

a random access memory with a command decode system including a core unit, said logic circuit and said random access memory with a command decode system being integrated into a single semiconductor chip; and

a random access memory control circuit receiving external control signals for said random access memory with a command decode system from said logic circuit, and outputting internal control signals to said core unit of said random access memory with a command decode system, wherein the internal control signals control said core unit of said random access memory with a command decode system.

11. The semiconductor integrated circuit device according to claim 10 further comprising:

external input terminal means for transmitting a first group of internal control signals for said random access memory with a command decode system; and

select means for supplying internal control signals to said core unit of said random access memory with a command decode system, the internal control signals being obtained by selecting either the first group of internal control signals received from said external input terminal means or a second group of internal control signals received from said random access memory with a command decode system, wherein said select means has a first mode selecting the first group of internal control signals received from said external input terminals for testing said semiconductor integrated circuit device with the first group of signals, and a second mode selecting the second group of internal control signals received from said random access memory with a command decode system.

12. The semiconductor integrated circuit device according to claim 10 further comprising:

external input terminal means for transmitting internal control signals for said random access memory with a command decode system;

synchronizing means for receiving the internal control signals from said external input terminal means and outputting a first group of internal control signals synchronized with a clock signal of said semiconductor integrated circuit; and

select means for supplying internal control signals to said core unit of said random access memory with a command decode system, the internal control signals being obtained by selecting either the first group of internal control signals received from said synchronizing means or a second group of internal control signals received from said random access memory with a command decode system, wherein said select means has a first mode selecting the first group of internal control signals received from said synchronizing means, and a second mode selecting the second group of internal control signals received from said random access memory with a command decode system.

13. The semiconductor integrated circuit device according to claim 10 further comprising:

external input terminal means for transmitting external control signals for said random access memory with a command decode system;

a command decoder for decoding the external control signals received from said external input terminal means into a first group of internal control signals for controlling said core unit of said random access memory with a command decode system; and

select means for supplying internal control signals to said core unit of said random access memory with a command decode system, the internal control signals being obtained by selecting either the first group of internal control signals received from said command decoder or a second group of internal control signals received from said random access memory with a command decode system, wherein said select means has a first mode selecting the first group of internal control signals received from said command decoder, and a second mode for selecting the second group of internal control signals received from said random access memory with a command decode system.

14. The semiconductor integrated circuit device according to claim 10 further comprising:

external input terminal means for transmitting external control signals for said random access memory with a command decode system;

synchronizing means for receiving the external control signals from said external input terminal means and outputting external control signals synchronized with a clock signal of said semiconductor integrated circuit;

a command decoder for decoding the external control signals received from said synchronizing means into a first group of internal control signals for controlling said core unit of said random access memory with a command decode system; and

select means for supplying internal control signals to said core unit of said random access memory with a command decode system, the internal control signals being obtained by selecting either the first group of internal control signals received from said command decoder or a second group of internal control signals received from said random access memory with a command decode system, wherein said select means has a first mode selecting the first group of internal control signals received from said command decoder and a second mode selecting the second group of internal control signals received from said random access memory with a command decode system.

15. The semiconductor integrated circuit device according to claim 10 further comprising:

external input terminal means for transmitting external control signals for said random access memory with a command decode system;

a command decoder for decoding the external control signals received from said external input terminal means into internal control signals for controlling said core unit of said random access memory with a command decode system;

synchronizing means receiving the internal control signals from said command decoder for outputting a first group of internal control signals synchronized with a clock signal of said semiconductor integrated circuit; and

select means for supplying the internal control signals to said core unit of said random access memory with a command decode system, the internal control signals being obtained by selecting either the first group of internal control signals received from said synchronizing means or a second group of internal control signals received from said random access memory with a command decode system, wherein said select means has a first mode selecting the first group of internal control signals received from said synchronizing means and a second mode selecting the second group of internal control signals received from said random access memory with a command decode system.

16. A method for testing a semiconductor integrated circuit device, said test method including, in a logic circuit and a random access memory with a command decode system including a core unit, said logic circuit and said random access memory with a command decode system being integrated into a single semiconductor chip:

providing external test signals through external input terminal means to a selector;

providing internal control signals from a random access memory with a command decode memory control system to a selector; and

selecting the external test signals from the external input terminal means, using the selector, and providing the selected signals to a core unit of said random access memory with a command decode system for testing, wherein the external test signals are external control signals for said core unit of said random access memory with a command decode system, and are decoded by a decoder to be the internal control signals provided to said selector.