High speed asynchronous and programmable state machine for generating almost full synchronous flags in a synchronous FIFO
View Patent ↗A state machine comprising a first input receiving a first read clock, a second input receiving a first write clock, a third input receiving a first programmable Almost Full look-ahead signal, a fourth input receiving a second read clock, a fifth input receiving a second write clock, and a sixth input receiving a second programmable Almost Full look-ahead signal is disclosed. The state machine manipulates the inputs to produce an output signal representing an Almost Full output flag that is at a first logic state when a FIFO is Almost Full and is at a second logic state when the FIFO is Not Almost Full.
1. An apparatus comprising:
a first set state machine configured to generate a first set-output signal that is either at a first logic state or at a second logic state in response to (i) a first read clock, (ii) a first write clock, (iii) a first programmable almost full look-ahead signal and (iv) a first control signal;
a second set state machine configured to generate a second set-output signal that is either at said first logic state or at said second logic state in response to (i) a second read clock, (ii) a second write clock, (iii) a second programmable almost full look-ahead signal and (iv) a second control signal;
a synchronizer configured to generate a synchronized output signal in response to said second set-output signal and a reset signal;
a latch configured to generate (i) a first latch output signal in response to said first set-output signal and said synchronized output signal and (ii) a second latch output signal as a complement of said first latch-output signal, said first latch output signal representing an almost full output flag that is at said first logic state when a FIFO (First In First Out) memory block is almost full, and is at said second logic state when said FIFO is not almost full;
a first logic block configured to generate said first control signal in response to said second latch output signal; and
a second logic block configured to generate (i) said reset signal and (ii) said second control signal in response to said first latch output signal.
2. The apparatus of claim 1 , wherein said synchronizer comprises:
a SR latch configured to time said second set-output signal depending on said reset signal; and
a Flip-Flop (FF) block configured to generate said synchronized signal depending on (i) an external timing signal and (ii) said second set-output signal as timed by said SR latch.
3. The apparatus of claim 2 , wherein said external timing signal comprises:
a free running write clock signal.
4. The apparatus of claim 1 , wherein said FIFO comprises:
a synchronous FIFO.
5. The apparatus of claim 1 , wherein said first write clock comprises:
a first enabled write clock.
6. The apparatus of claim 1 , wherein said first read clock comprises:
a first enabled read clock.
7. The apparatus of claim 1 , wherein said second write clock comprises:
a second enabled write clock.
8. The apparatus of claim 1 , wherein said second read clock comprises:
a second enabled read clock.
9. The apparatus of claim 1 further comprising:
a first delay block configured to increase a first pulse width of said first latch output signal before said second logic block.
10. The apparatus of claim 9 further comprising:
a second delay block configured to increase a second pulse width of said second latch output signal before said first logic block.
11. The apparatus of claim 10 , wherein said second delay block has a second predetermined delay configured during fabrication.
12. The apparatus of claim 10 , wherein said second delay block comprises:
a programmable delay block configured to change said second pulse width.
13. The apparatus of claim 10 , wherein said second delay block comprises:
a programmable delay block responsive to an externally generated signal.
14. The apparatus of claim 13 , wherein said programmable delay block further comprises:
a joint test access group (JTAG) programmable delay block.
15. The apparatus of claim 14 , wherein a set of additional JTAG instructions are utilized to program said JTAG programmable delay block.
16. The apparatus of claim 9 , wherein said first delay block has a predetermined delay configured during fabrication.
17. The apparatus of claim 9 , wherein said first delay block comprises:
a programmable delay block configured to change said first pulse width.
18. The apparatus of claim 9 , wherein said first delay block comprises:
a programmable delay block responsive to an externally generated signal.
19. The apparatus of claim 18 , wherein said programmable delay block comprises:
a joint test access group (JTAG) programmable delay block.
20. The apparatus of claim 19 , wherein a set of additional JTAG instructions are utilized to program said JTAG programmable delay block.
21. An apparatus comprising:
means for generating a first output signal either at a first logic state or at a second logic state in response to (i) a first read clock, (ii) a first write clock, (iii) a first programmable almost full look-ahead signal and (iv) a first control signal;
means for generating a second output signal either at said first logic state or at said second logic state in response to (i) a second read clock, (ii) a second write clock, (iii) a second programmable almost full look-ahead signal and (iv) a second control signal;
means for generating a synchronized output signal in response to (i) said second output signal and (ii) a reset signal;
means for generating (i) a first latch output signal representing an almost full output flag that is at a first logic state when a FIFO memory block is almost full and is at a second logic state when said FIFO is not almost full, in response to said first output signal and said synchronized output signal and (ii) a second latch output signal as a complement of said first latch output signal;
means for generating said first control signal in response to said second latch output signal; and
means for generating (i) said second control signal and (ii) said reset signal in response to said first latch output signal.
22. The apparatus of claim 21 further comprising:
means for increasing a pulse width of said first latch output signal.
23. The apparatus of claim 21 further comprising:
means for increasing a pulse width of said second latch output signal.