IP Library Granted Patent US 7,257,661
Granted Patent B2
US 7,257,661 · App. 09/961,125 · Granted Aug 14, 2007

Scalable home control platform and architecture

Assignee: NXP B.V.
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Quick Facts
Patent No.
US 7,257,661
App. No.
09/961,125
Granted
Aug 14, 2007
Kind
B2
Abstract

A home-control platform and architecture includes a plurality of serial buses that provide communications among processing devices that are connected to the home-control platform. A bus control unit is configured to allocate the buses among the devices that request communications services. The platform supports one or more control processors that provide an interface to legacy devices, user and network interfaces, browsers, and the like. The platform also accepts optional plug-in cards that perform as coprocessors for specific tasks, such as MPEG encoding and decoding, signal processing, video and audio CODECs, and so on. The software architecture employed to support this platform includes the use of a real-time microkernel Operating System (OS) at the control processors that interfaces with the task coprocessors, and interfaces with a standard OS, such as Vxworks, WinCE, or LINUX. The microkernel OS provides primitives for task memory and CPU space isolation, virus protection, and secure financial transaction services.

Claims (17)

1. A scalable home-control system and network, comprising:

a platform ( 100 ) providing for a grouping of processing devices ( 110 ), control processors ( 120 ), and ancillary units ( 130 ) on plug-in cards;

a plurality of serial data busses ( 150 ) disposed in the platform ( 100 ) and arranged in parallel as a single, extendable communications backbone for the platform, and such that data traffic can be split across one or more of the serial buses ( 150 ), and each serial bus ( 150 ) includes a self-timing mechanism to enable bandwidth and data throughput scalability;

a plurality of plug-in slot connectors with each such slot connected in parallel across each and all of the plurality of serial buses, and thereby provide a hot swappable plug-in point for each plug-in card;

a bus controller ( 210 ) for using one of said serial buses ( 150 ) as a control channel, and providing for device allocations to use said control channel to request and be granted the exclusive use of any other of the other serial buses, wherein a resource allocation for one application can be accommodated without impacting any other allocations;

a bus interface controller ( 160 ) provided on said plug-in cards, and providing for the sending and receiving of data over selected ones of said serial buses ( 150 ) that have been allocated to it by the bus controller ( 210 );

a plurality of filter processors ( 115 ) disposed in said processing devices ( 110 ) and arranged in a routing matrix, and connected to a corresponding bus interface controller ( 160 ), herein each filter processor ( 115 ) performs a particular task on a data item and passes it to a next filter processor ( 115 ) in lock-step fashion; and

a user interaction device ( 360 ) for locally communicating commands and status with a user, and interfaced with at least one of the processing devices( 110 );

wherein, such is configured to support legacy devices in existing home control networks.

2. The system and network of claim 1 , further comprising:

an ancillary unit ( 130 ) including electro-optic couplers providing for platform extensions to other groupings of processing devices ( 110 ), control processors ( 120 ), and ancillary units ( 130 ) on plug-in cards in other platforms ( 100 ).

3. The system and network of claim 1 , further comprising:

a control processor ( 120 ) providing for an interface to legacy devices ( 301 - 304 ) to the rest of the system.

4. The system and network of claim 3 , further comprising:

a real-time microkernel ( 510 ) included in the control processor ( 120 ), and providing for operating system functions that include semaphores, messaging, scheduling, exception and task and memory management, and providing for interfaces to task processors and standard operating systems.

5. The system and network of claim 4 , further comprising:

a coprocessor interface layer ( 520 ) that provides the interface between the micromere ( 510 ) and any filter programs ( 530 ) disposed in said processing devices ( 110 ), wherein any task applications ( 540 , 550 ) have direct access to said filter programs ( 530 ) via interface layer ( 520 ).

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2012
From: TRIDENT MICROSYSTEMS, INC.; TRIDENT MICROSYSTEMS (FAR EAST) LTD.
To: ENTROPIC COMMUNICATIONS, INC.
Reel/Frame 028153/0530 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2010
From: NXP
To: NXP HOLDING 1 B.V.
Reel/Frame 023928/0489 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2010
From: TRIDENT MICROSYSTEMS (EUROPE) B.V.; NXP HOLDING 1 B.V.
To: TRIDENT MICROSYSTEMS (FAR EAST) LTD.
Reel/Frame 023928/0552 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2007
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 019719/0843 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 21, 2001
From: O'DONNELL, CLARAN GERARD
To: KONINKLIJKE PHILIPS ELECTRONICS N.V.
Reel/Frame 012194/0547 →
Continuity (1)
Related Publication 20030061427A1 · Mar 27, 2003