Granted Patent B2

US 7,062,005 · App. 10/142,854 · Granted Jun 13, 2006

Abstract

Claims (28)

1. A system for synchronising slave and master timing, comprising:

a phase adjust circuit for receiving and delaying an arbitrary clock signal by an adjustable amount and outputting a delayed clock signal related to said slave timing; and

a master phase detector and lock circuit for comparing relative phases of said master and slave timing and in response generating and applying delay adjust signals to said phase adjust circuit at a dynamically adjusted rate which is related to said relative phases in order to synchronise said slave and master timing and is thereafter reduced to a minimum rate required to maintain synchronisation of said slave and master timing;

wherein said master phase detector includes circuitry for generating said delay adjust signals in the form of up count signals for incrementally increasing said adjustable amount of delay in the event said slave timing leads said master timing, and down count signals for incrementally decreasing said adjustable amount of delay in the event said slave timing lags said master timing.

2. The system of claim 1 , wherein said master phase detector and lock circuit further includes:

an upper limit counter for generating an upper limit count value which is related to said dynamically adjusted rate at which said delay adjust signals are applied to said phase adjust circuit by an inverse piece-wise linear exponential relationship;

an up counter for counting how many of said up count signals are generated within a predetermined sample period;

a down counter for counting how many of said down count signals are generated within said predetermined sample period; and

a count compare circuit for generating an up/down signal which (i) decrements said upper limit counter in the event either of said up counter or down counter has counted to no greater than a predetermined number, thereby doubling said dynamically adjusted rate at which said delay adjust signals are applied to said phase adjust circuit, and (ii) increments said upper limit counter in the event that both said up counter and down counter have counted to greater than said predetermined number and the numerical average of said up counter and down counter exceeds the absolute value of their difference by at least said predetermined number, thereby halving said dynamically adjusted rate at which said delay adjust signals are applied to said phase adjust circuit.

3. The system according to claim 2 , further comprising a frequency hold over circuit for calculating a steady-state rate at which said delay adjust signals are applied to said phase adjust circuit while maintaining said synchronisation of said slave and master timing and than applying said delay adjust signals to said phase adjust circuit at said steady-state rate.

4. The system of claim 2 , wherein said predetermined number is chosen to minimize said up counter and down counter to count values greater than zero.

5. The system according to claim 4 , further comprising a frequency hold over circuit for calculating a steady-state rate at which said delay adjust signals are applied to said phase adjust circuit while maintaining said synchronisation of said slave and master timing and than applying said delay adjust signals to said phase adjust circuit at said steady-state rate.

6. The system of claim 4 , wherein said predetermined number is five.

7. The system according to claim 6 , further comprising a frequency hold over circuit for calculating a steady-state rate at which said delay adjust signals are applied to said phase adjust circuit while maintaining said synchronisation of said slave and master timing and than applying said delay adjust signals to said phase adjust circuit at said steady-state rate.

8. The system according to claim 1 , further comprising a frequency hold over circuit for calculating a steady-state rate at which said delay adjust signals are applied to said phase adjust circuit while maintaining said synchronisation of said slave and master timing and than applying said delay adjust signals to said phase adjust circuit at said steady-state rate.

9. A method of synchronising slave and master timing, comprising:

delaying an arbitrary clock signal by an adjustable amount and outputting a delayed clock signal related to said slave timing;

comparing relative phases of said master and slave timing and in response generating delay adjust signals for decreasing said adjustable amount of delay in the event said slave timing lags said master timing and increasing said adjustable amount of delay in the event said slave timing leads said master timing; and

dynamically adjusting the rate at which said delay adjust signals are generated relative to said relative phases in order to synchronise said slave and master timing and thereafter reducing said rate to a value required to maintain synchronisation of said slave and master timing.

10. The method of claim 9 , wherein said delay adjust signals are generated in the form of up count signals for incrementally increasing said adjustable amount of delay, and down count signals for incrementally decreasing said adjustable amount of delay.

11. The method according to claim 10 , further comprising calculating a stead-state rate at which said delay adjust signals are generated while maintaining said synchronisation of said slave and master timing and then generating said delay adjust signals at said steady-state rate.

12. The method of claim 10 , further comprising: generating an upper limit count value which is related to said dynamically adjusted rate at which said delay adjust signals are generated by an inverse piece-wise linear exponential relationship; counting the number of said up count signals generated within a predetermined sample period; counting the number of said down count signals generated within said predetermined sample period; and generating an up/down signal which (i) decrements said upper limit count value in the event either of said number of up count or down count signals is no greater than a predetermined number, thereby doubling said dynamically adjusted rate at which said delay adjust signals are generated, and (ii) increments said upper limit count value in the event that both said number of up count signals and said number of down count signals are greater than said predetermined number and the numerical average of said number of up count signals and said number of down count signals exceeds the absolute value of their difference by at least said predetermined number, thereby halving said dynamically adjusted rate at which said delay adjust signals are generated.

13. The method according to claim 12 , further comprising calculating a steady-state rate at which said delay adjust signals are generated while maintaining said synchronisation of said slave and master timing and then generating said delay adjust signals at said steady-state rate.

14. The method of claim 12 , wherein said predetermined number is chosen to minimize said numbers of up count signals and down count signals to an amount which is greater than zero.

15. The method according to claim 14 , further comprising calculating a steady-state rate at which said delay adjust signals are generated while maintaining said synchronisation of said slave and master timing and then generating said delay adjust signals at said steady-state rate.

16. The method of claim 14 , wherein said predetermined number is five.

17. The method according to claim 16 , further comprising calculating a steady-state rate at which said delay adjust signals are generated while maintaining said synchronisation of said slave and master timing and then generating said delay adjust signals at said steady-state rate.

18. The method according to claim 9 , further comprising calculating a steady-state rate at which said delay adjust signals are generated while maintaining said synchronisation of said slave and master timing and then generating said delay adjust signals at said steady-state rate.

Assignments (17)