Method and device for synchronizing a radio transmitter with a radio receiver
View Patent ↗A method and a device are proposed for the synchronization of a radio transmitter and a radio receiver, notably for UMTS, while utilizing a Golay correlator, which synchronization should be performed reliably without imposing severe requirements as regards the frequency stability of the local oscillator. To this end, absolute value squaring B 1 , B 2 is performed in the Golay correlator already prior to the last delay stages (D 7, D 8 ).
1. A method of performing chip synchronization of a radio transmitter and a radio receiver using a Golay correlator comprising a sequence of stages including complex stages, wherein in each of a plurality of said complex stages at least one sum is formed of a complex output signal from a prior stage delayed by a delay stage and a complex output signal from the prior stage multiplied by a weighting factor, the method comprising:
performing absolute value squaring of output signals of an intermediate stage prior to a final delay stage to produce a pair of real-valued output signals; and
processing the real-valued output signals in one or more additional stages, wherein in each of the additional stages at least one sum is formed of an output signal from a prior stage delayed by a delay stage and an output signal from the prior stage multiplied by a weighting factor.
2. A method as claimed in claim 1 , wherein the absolute value squaring is performed prior to a next-to-last delay stage.
3. A method as claimed in claim 1 , wherein a delay stage of one of said additional stages implements a delay corresponding to a sub-length of 64 chips of a synchronization signal sequence comprising 256 chips.
4. A Golay correlator for performing chip synchronization comprising:
a sequence of stages including complex stage, wherein in each of a plurality of said complex stages at least one sum is formed of a complex output signal from a prior stage delayed by a delay stage and a complex output signal from the prior stage multiplied by a weighting factor;
absolute value squarers for performing absolute value squaring of output signals of an intermediate stage prior to a final delay stage to produce a pair of real-valued output signals;
one or more additional stages for processing the real-valued output signals, wherein in each of the additional stages at least one sum is formed of an output signal from a prior stage delayed by a delay stage and an output signal from the prior stage multiplied by a weighting factor; and
means for bypassing the absolute value squarers and switching operation of the additional stages from real to complex.
5. A device as claimed in claim 4 , wherein weighting factors applied to the additional stages are equal in “1”.
6. A method of performing chip synchronization of a radio transmitter and a radio receiver using a Golay correlator comprising a sequence of stage including complex stages, wherein in each of a plurality of said complex stages at least one sum is formed of a complex output signal from a prior stage delayed by a delay stage and a complex output signal from the prior stage multiplied by a weighting factor, the method comprising:
in one mode;
performing absolute value squaring of output signals of an intermediate stage prior to a final Golay stage to produce a pair of real-valued output signals; and
processing the real-valued output signals in one or more additional stages, wherein in each of the additional stages at least one sum is formed of an output signal from a prior stage delayed by a delay stage and an output signal from the prior stage multiplied by a weighting factor; and
in another mode;
performing absolute value squaring of output signals of a final stage to produce a real-valued output signal indicative of a degree of correlation between received data and a synchronization sequence.
7. The method as claimed in claim 6 , comprising, in said another mode of operation:
bypassing absolute value squarers that would otherwise performing absolute value squaring of output signals of an intermediate stage prior to a final delay stage; and
switching operation of the additional stages from real to complex.