Receiver of frequency-modulated signals with digital demodulator

1. A receiver of a frequency-modulated signal representing a digital signal comprising:

a frequency translation unit comprising

a single local oscillator including a divider, wherein the single local oscillator generates both a local oscillator signal and a reference signal, the reference signal having a frequency derived by the divider dividing a frequency of the local oscillator signal by a value, and

a mixer circuit that multiplies the received frequency-modulated signal with the local oscillator signal to lower the frequency of the received frequency-modulated signal to provide a lowered-frequency signal;

a digital demodulator to regenerate the digital signal from the lowered-frequency signal, wherein the frequency translation unit comprises counting means to determine the number of periods of the reference signal during a period of the lowered-frequency signal and wherein the digital demodulator comprises computation means to compute the period of the lowered-frequency signal from the number of periods of the reference signal; and

wherein the duration of the period of the reference signal is variable and may take two possible values, T 1 and T 2 ; and further

wherein the counting means comprises a first counter to count a number P of periods with a duration T 1 of the reference signal during a period of the lowered-frequency signal and a second counter to count a number Q of periods with a duration T 2 of the reference signal during a period of the lowered-frequency signal, and wherein the computation means of the digital demodulator computes the period of the lowered-frequency signal by adding the number of P periods and the number of Q periods.

2. A receiver according to claim 1 , wherein the digital demodulator further comprises means to convert the lowered-frequency signal into a logic signal and means to detect the leading edges of the logic signal, the first and second counters being reset at each leading edge of the logic signal.

3. A receiver according to claim 1 , wherein the digital demodulator further comprises means to convert the lowered-frequency signal into a logic signal and means to detect the trailing edges of the logic signal, the first and second counters being reset at each trailing edge of the logic signal.

4. A receiver according to claim 1 , made in the form of an integrated circuit.

5. An electrical circuit comprising:

a receiver circuit for receiving a frequency-modulated signal representing a digital signal;

a frequency translation unit, electrically coupled to the receiver circuit, comprising a single local oscillator that generates both a local oscillator signal and a reference signal having a frequency derived by a divider in the single local oscillator dividing a frequency of the local oscillator signal by a value N, and a mixer circuit that multiplies the received frequency-modulated signal with the local oscillator signal for lowering the frequency of the received frequency-modulated signal to provide a lowered-frequency signal;

a digital demodulator, electrically coupled to the frequency translation unit, for regenerating the digital signal from the lowered-frequency signal;

counting means, electrically coupled to the receiver circuit and to the frequency translation unit, for determining the number of periods of the reference signal during a period of the lowered-frequency signal;

computation means, electrically coupled to the digital demodulator, for computing the period of the lowered-frequency signal from the number of periods of the reference signal; and

wherein the duration of the period of the reference signal is variable and may take two possible values, T 1 and T 2 ; and further

wherein the counting means comprises:

a first counter to count a number P of periods with a duration T 1 of the reference signal during a period of the lowered-frequency signal; and

a second counter to count a number Q of periods with a duration T 2 of the reference signal during a period of the lowered-frequency signal, and wherein the computation means computes the period of the lowered-frequency signal by adding the number of P periods and the number of Q periods.

6. The electrical circuit of claim 5 , wherein the digital demodulator comprises:

means to convert the lowered-frequency signal into a logic signal; and

means to detect the leading edges of the logic signal.

7. The electrical circuit of claim 5 , wherein the first and second counters are reset at each leading edge of the logic signal.

8. The electrical circuit of claim 5 , wherein the digital demodulator further comprises means to convert the lowered-frequency signal into a logic signal and means to detect the trailing edges of the logic signal.

9. The electrical circuit of claim 5 , wherein the first and second counters are reset at each trailing edge of the logic signal.

10. The electrical circuit of claim 5 , made in the form of an integrated circuit.

11. The electrical circuit of claim 5 , in which N is an integer.

12. A frequency-modulated signal receiver integrated circuit comprising:

a receiver circuit for receiving a frequency-modulated signal representing a digital signal;

a frequency translation unit, electrically coupled to the receiver circuit, comprising a single local oscillator that generates a local oscillator signal and a reference signal having a frequency derived by a divider in the single local oscillator dividing a frequency of the local oscillator signal by a value N, and a mixer circuit that multiplies the frequency-modulated signal with the local oscillator signal for lowering the frequency of the received frequency-modulated signal to provide a lowered-frequency signal;

a digital demodulator, electrically coupled to the frequency translation unit, for regenerating the digital signal from the lowered-frequency signal;

a reference signal generator, electrically coupled to the frequency translation unit, for providing a reference signal from the single local oscillator to the digital demodulator, and wherein the duration of the period of the reference signal is variable and may take two possible values, T 1 and T 2 ;

counting means, electrically coupled to the receiver circuit, to the reference signal generator and to the frequency translation unit, for determining the number of periods of the reference signal from the frequency translation unit during a period of the lowered-frequency signal;

computation means, electrically coupled to the digital demodulator, for computing the period of the lowered-frequency signal from the number of periods of the reference signal;

a first counter for counting a number P of periods with a duration T 1 of the reference signal during a period of the lowered-frequency signal; and

a second counter for counting a number Q of periods with a duration T 2 of the reference signal during a period of the lowered-frequency signal, and wherein the computation means computes the period of the lowered-frequency signal by adding the number of P periods and the number of Q periods.

13. The frequency-modulated signal receiver integrated circuit of claim 12 , in which N is an integer.