Granted Patent B2

US 6,844,793 · App. 10/204,992 · Granted Jan 18, 2005

Abstract

Claims (39)

1. A signal combiner having a plurality of signal input paths, wherein each signal path comprises an input impedance transformer and a switch configured to selectively connect the input of the transformer to a predetermined impedance, the outputs of the impedance transformers being connected in a summing configuration and the impedance transformers being arranged in a ladder arrangement, wherein:

the signal combiner has a nominal operating frequency having a wavelength λ;

each signal transformer is formed by a transmission line having a length of λ(2k+1)/4, where k is a positive integer, including zero; and

there are N input channels and N impedance transformers, each connecting to an nth node, where n is an integer in the range 1 to N and the nth node is connected to the (n−1)th node by an (n−1)th linking arrangement.

2. The signal combiner of claim 1 , wherein the switch associated with an input of an impedance transformer is arranged to connect the input to ground.

3. The signal combiner of claim 1 , wherein each linking arrangement is a quarter wavelength transmission line.

4. An electronic device comprising a splitter, a plurality of signal processing devices receiving input signals from the splitter, and a combiner configure to combine the outputs of the signal processing devices, wherein:

the combiner has a plurality of signal input paths; and

each signal path comprises an input impedance transformer and a switch configured to selectively connect the input of the transformer to a predetermined impedance, the outputs of the impedance transformers being connected in a summing configuration and the impedance transformers being arranged in a ladder arrangement, wherein:

the splitter has an input and a plurality of outputs, and the signal at the input is divided equally between the outputs; and

the nth output of the splitter, where n is a positive non zero integer, is associated with a delay element, wherein the delay expressed in terms of wavelength is (nλ)/4.

5. The electronic device of claim 4 , wherein each output of the splitter is selectively connected to either an associated signal processing device or a matched load.

6. A combined splitter and phase compensation vice for use with a combiner, wherein the combined splitter and phase compensation device has N output channels, and the phase difference between an nth channel and an (n−1)th channel is λ/4 where n is an integer in the range 1 to N and wherein the combiner is of a type having a plurality of signal input paths, wherein each signal path comprises an input impedance transformer and a switch configured to selectively connect the input of the transformer to a predetermined impedance, the outputs of the impedance transformers being connected in a summing configuration and the impedance transformers being arranged in a ladder arrangement.

7. An apparatus, comprising N signal paths, wherein:

the input of an nth signal path is adapted to receive an nth input signal, where n is an integer in the range 1 to N, and N is an integer greater than 1;

each signal path comprises a series combination of one or more elements that introduce signal delay and an active component, wherein total signal delay from the signal path input to the signal path output is different for at least two of the signal paths; and

for each n>1, the output of the nth signal path is connected to the output of the (n−1)th signal path by an (n−1)th linking element, wherein the total signal delay from the input of each signal path to the output of the Mth signal path is substantially equal for all N signal paths, where M is integer in the range 1 to N.

8. The invention of claim 7 , wherein:

the active component is an amplifier;

the total signal delay from the signal path input to the signal path output is different for each different signal path; and

M is equal to N.

9. The invention of claim 7 , wherein the nth signal path comprises:

an nth delay element connected to receive the nth input signal;

for n=1, an nth impedance transforming element connected at its output to the input of the nth linking element; and

for each n>1, an nth impedance transforming element connected at its output to the output of the (n−1)th linking element; and

an nth active component connected at its output to the input of the nth impedance transforming element.

10. The invention of claim 9 , wherein:

all N delay elements are adapted to introduce different signal delays; and

all N impedance transforming elements are adapted to introduce a substantially identical signal delay.

11. The invention of claim 10 , wherein:

the nth delay element is adapted to introduce a signal delay of about (nλ)/4, when expressed in terms of wavelength λ;

each impedance transforming element is adapted to introduce a signal delay o about λ/4; and

each linking element is adapted to introduce a signal delay of about λ/4.

12. The invention of claim 9 , wherein each signal path further comprises a switch adapted to selectively couple the input of the corresponding impedance transforming element to ground.

13. The invention of claim 9 , wherein each signal path further comprises a switch adapted to selectively couple the output of the corresponding delay element to a matched load instead of to the corresponding active component.

14. The invention of claim 13 , wherein each signal path further comprises another switch adapted to selectively couple the input of the corresponding impedance transforming element to ground.

15. The invention of claim 7 , further comprising a splitter adapted to provide the N input signals to the N signal paths.

16. The invention of claim 15 , wherein the signal paths are interconnected only through the splitter and the linking elements.

17. The invention of claim 15 , wherein the N input signals are substantially identical.

Assignments (11)