Main memory controller adapted to correct corrupted data by xoring corrupted data to directly generate correct data

1. A memory controller adapted to configure a semiconductor main memory as a fault tolerant memory array, the memory controller comprising:

a memory bus interface adapted to be coupled to the semiconductor main memory for direct access to the semiconductor main memory;

a local bus interface adapted to be coupled to a central processing unit;

wherein the memory controller is adapted to utilize error correction code to detect corrupted data retrieved by the memory controller from the semiconductor main memory; and

wherein the memory controller is further adapted to correct the corrupted data by XORing the corrupted data to directly generate correct data.

2. The memory controller, as set forth in claim 1 , wherein the semiconductor main memory comprises a plurality of memory modules.

3. The memory controller, as set forth in claim 2 , wherein the memory controller is adapted to configure the semiconductor main memory to stripe data across the plurality of memory modules such that each stripe comprises a plurality of blocks of data and at least one block of parity information, each of the plurality of blocks of data and the at least one block of parity information adapted to be stored in a respective one of the plurality of memory modules.

4. The memory controller, as set forth in claim 2 , wherein the plurality of memory modules are removable.

5. The memory controller, as set forth in claim 1 , wherein the XOR engine is adapted to retrieve a plurality of blocks of data and at least one block of parity information from the semiconductor main memory and to correct corrupted data in one of the plurality of blocks of data by XORing the other plurality of blocks of data and the at least one block of parity information.

6. The memory controller, as set forth in claim 1 , wherein the XOR engine is adapted to restore the corrected data to the semiconductor main memory.

7. A memory system comprising:

a semiconductor main memory;

a memory controller adapted to be used as a bridge between at least one processor and the semiconductor main memory;

wherein the memory controller is adapted to be operably coupled to the semiconductor main memory for direct access to the semiconductor main memory;

wherein the memory controller is adapted to configure the semiconductor main memory as a fault tolerant memory array;

wherein the memory controller is adapted to utilize error correction code to detect corrupted data retrieved by the memory controller from the semiconductor main memory; and

wherein the memory controller is further adapted to correct the corrupted data by XORing the corrupted data to directly generate correct data.

8. The memory system, as set forth in claim 7 , wherein the semiconductor main memory comprises a plurality of memory modules.

9. The memory system, as set forth in claim 8 , wherein the memory controller is adapted to configure the semiconductor main memory to stripe data across the plurality of memory modules such that each stripe comprises a plurality of blocks of data and at least one block of parity information, each of the plurality of blocks of data and the at least one block of parity information adapted to be stored in a respective one of the plurality of memory modules.

10. The memory system, as set forth in claim 8 , wherein the plurality of memory modules are removable.

11. The memory system, as set forth in claim 7 , wherein the XOR engine is adapted to retrieve a plurality of blocks of data and at least one block of parity information from the semiconductor main memory and to correct corrupted data in one of the plurality of blocks of data by XORing the other plurality of blocks of data and the at least one block of parity information.

12. The memory system, as set forth in claim 7 , wherein the XOR engine is adapted to restore the corrected data to the semiconductor main memory.

13. A computer system comprising:

a semiconductor main memory adapted to store data;

a processor adapted to request that the data be stored in the semiconductor main memory and read from the semiconductor main memory;

a memory controller configured to directly access the semiconductor main memory in response to interaction with the processor;

secondary non-volatile memory indirectly accessible by the memory controller through a peripheral device bus;

wherein the memory controller is operably coupled to the semiconductor main memory and is adapted to configure the semiconductor main memory as a fault tolerant memory array;

wherein the memory controller is adapted to utilize error correction code to detect corrupted data retrieved by the memory controller from the semiconductor main memory; and

wherein the memory controller is further adapted to correct the corrupted data by XORing the corrupted data to directly generate correct data.

14. The computer system, as set forth in claim 13 , wherein the semiconductor main memory comprises a plurality of memory modules.

15. The computer system, as set forth in claim 14 , wherein the memory controller is adapted to configure the semiconductor main memory to stripe data across the plurality of memory modules such that each stripe comprises a plurality of blocks of data and at least one block of parity information, each of the plurality of blocks of data and the at least one block of parity information adapted to be stored in a respective one of the plurality of memory modules.

16. The computer system, as set forth in claim 14 , wherein the plurality of memory modules are removable.

17. The computer system, as set forth in claim 13 , wherein the XOR engine is adapted to retrieve a plurality of blocks of data and at least one block of parity information from the semiconductor main memory and to correct corrupted data in one of the plurality of blocks of data by XORing the other plurality of blocks of data and the at least one block of parity information.

18. The computer system, as set forth in claim 13 , wherein the XOR engine is adapted to restore the corrected data to the semiconductor main memory.

19. A memory controller adapted to configure a semiconductor main memory as a fault tolerant memory array in which data is stored in stripes, each of the stripes comprising a plurality of blocks of data and at least one block of parity information, the memory controller comprising:

a memory bus interface adapted to be coupled to the semiconductor main memory for direct access to the semiconductor main memory;

a local bus interface adapted to be coupled to a central processing unit;

wherein each of the plurality of blocks of data and the at least one block of parity information are stored in respective segments of the semiconductor main memory;

wherein the memory controller is adapted to utilize error correction code to detect corrupted data in a stripe retrieved by the memory controller from the semiconductor main memory; and

wherein the memory controller is further adapted to correct the corrupted data in the stripe by XORing the data stored in the other stripes to generate correct data in the corrupted stripe.

20. The memory controller, as set forth in claim 19 , wherein the semiconductor main memory comprises a plurality of memory modules.

21. The memory controller, as set forth in claim 20 , wherein the memory controller is adapted to configure the semiconductor main memory to stripe data across the plurality of memory modules such that each of the plurality of blocks of data and the at least one block of parity information are adapted to be stored in a respective one of the plurality of memory modules.

22. The memory controller, as set forth in claim 19 , wherein the plurality of memory modules are removable.

23. The memory controller, as set forth in claim 19 , wherein the XOR engine is adapted to retrieve a plurality of blocks of data and at least one block of parity information from the semiconductor main memory and to correct corrupted data in one of the plurality of blocks of data by XORing the other plurality of blocks of data and the at least one block of parity information.

24. The memory controller, as set forth in claim 19 , wherein the XOR engine is adapted to restore the corrected data to the semiconductor main memory.

25. A memory system comprising:

a semiconductor main memory;

a memory controller adapted to be used as a bridge between at least one processor and the semiconductor main memory;

wherein the memory controller is adapted to be operably coupled to the semiconductor main memory for direct access to the semiconductor main memory;

wherein the memory controller is adapted to configure the semiconductor main memory as a fault tolerant memory array in which data is stored in stripes, each of the stripes comprising a plurality of blocks of data and at least one block of parity information;

wherein each of the plurality of blocks of data and the at least one block of parity information are stored in respective segments of the semiconductor main memory;

wherein the memory controller is adapted to utilize error correction code to detect corrupted data in a stripe retrieved by the memory controller from the semiconductor main memory; and

wherein the memory controller is further adapted to correct the corrupted data in the stripe by XORing the data stored in the other stripes to generate correct data in the corrupted stripe.

26. The memory system, as set forth in claim 25 , wherein the semiconductor main memory comprises a plurality of memory modules.

27. The memory system, as set forth in claim 26 , wherein the memory controller is adapted to configure the semiconductor main memory to stripe data across the plurality of memory modules such that each of the plurality of blocks of data and the at least one block of parity information are adapted to be stored in a respective one of the plurality of memory modules.

28. The memory system, as set forth in claim 26 , wherein the plurality of memory modules are removable.

29. The memory system, as set forth in claim 25 , wherein the XOR engine is adapted to retrieve a plurality of blocks of data and at least one block of parity information from the semiconductor main memory and to correct corrupted data in one of the plurality of blocks of data by XORing the other plurality of blocks of data and the at least one block of parity information.

30. The memory system, as set forth in claim 25 , wherein the XOR engine is adapted to restore the corrected data to the semiconductor main memory.

31. A computer system comprising:

a semiconductor main memory adapted to store data;

a processor adapted to request that the data be stored in the semiconductor main memory and read from the semiconductor main memory;

a memory controller configured to directly access the semiconductor main memory in response to interaction with the processor;

secondary non-volatile memory indirectly accessible by the memory controller through a peripheral device bus;

wherein the memory controller is adapted to configure the semiconductor main memory as a fault tolerant memory array in which data is stored in stripes, each of the stripes comprising a plurality of blocks of data and at least one block of parity information;

wherein each of the plurality of blocks of data and the at least one block of parity information are stored in respective segments of the semiconductor main memory;

wherein the memory controller is adapted to utilize error correction code to detect corrupted data in a stripe retrieved by the memory controller from the semiconductor main memory; and

wherein the memory controller is further adapted to correct the corrupted data in the stripe by XORing the data stored in the other stripes to generate correct data in the corrupted stripe.

32. The computer system, as set forth in claim 31 , wherein the semiconductor main memory comprises a plurality of memory modules.

33. The computer system, as set forth in claim 32 , wherein the memory controller is adapted to configure the semiconductor main memory to stripe data across the plurality of memory modules such that each of the plurality of blocks of data and the at least one block of parity information are adapted to be stored in a respective one of the plurality of memory modules.

34. The computer system,as set forth in claim 32 , wherein the plurality of memory modules are removable.

35. The computer system, as set forth in claim 31 , wherein the XOR engine is adapted to retrieve a plurality of blocks of data and at least one block of parity information from the semiconductor main memory and to correct corrupted data in one of the plurality of blocks of data by XORing the other plurality of blocks of data and the at least one block of parity information.

36. The computer system, as set forth in claim 31 , wherein the XOR engine is adapted to restore the corrected data to the semiconductor main memory.