Method and arrangement for automatic frequency correction
View Patent ↗A method and arrangement for automatic frequency correction in UTRA TDD mode, having a first stage ( 500 ) for frequency lock in idle mode, and a second stage ( 600 ) for receiving a channel estimate from beacon function (mx 1 ), receiving a channel estimate from at least one other physical channel (mx 2 ), and receiving output from a primary synchronisation code correlator (mx 0 , pc 1 , pc 2 ), and for producing therefrom signals (X,Y,N) for use in frequency correction. By utilising first and second partial correlation values (pc 1 , pc 2 ) which are balanced, DC offset effects may be substantially removed. This provides the following advantage of significantly improving performance at low levels of SNR, and removal of DC offset effects provides immunity to DC offsets arising from imperfections in hardware.
1. A method for automatic frequency correction in UTRA TDD mode, the method comprising:
performing a frequency lock with a signal including received samples;
receiving a channel estimate from a beacon function;
receiving a channel estimate from at least one other physical channel;
receiving output from a primary synchronization code correlator;
producing therefrom signals for use in frequency correction; and
applying said signals to a variable-frequency signal generator.
2. The method of claim 1 , wherein performing a frequency lock comprises performing a frequency lock in idle mock.
3. The method of claim 1 , wherein performing a frequency lock comprises:
performing a first frequency lock at a relatively wide bandwidth; and
performing a second frequency lock at a relatively narrow bandwidth.
4. The method of claim 1 wherein performing a frequency lock comprises confirming frequency lock.
5. The method of claim 1 wherein producing signals for use in frequency correction comprises utilizing first and second partial correlation values which are balanced so as to substantially remove DC offset effects.
6. An arrangement for automatic frequency correction in UTRA TDD mode, the arrangement comprising:
means for performing a frequency lock with a signal including received samples;
means for receiving a channel estimate from a beacon function, receiving a channel estimate from at least one other physical channel, receiving output from a primary synchronization code correlator, and producing therefrom signals for use in frequency correction.
7. The arrangement of claim 6 , wherein the means for performing a frequency lock comprises means for performing a frequency lock in idle mode.
8. The arrangement of claim 6 , wherein the means for performing a frequency lock comprises:
means for performing a first frequency lock at a relatively wide bandwidth; and
means for performing a second frequency lock at a relatively narrow bandwidth.
9. The arrangement of claim 6 , wherein the means for performing a frequency lock comprises means for confirming frequency lock.
10. The arrangement of claim 6 , wherein the means for producing signals for use in frequency correction comprises means for utilizing first and second partial correlation values which are balanced so as to substantially remove DC offset effects.
11. The arrangement of claim 6 , wherein the arrangement resides in user equipment for use in a UMTS system.
12. A computer readable medium comprising computer program code for performing automatic frequency correction as claimed in claim 1 .