Method and arrangement for sample-rate conversion

1. A method of converting the sample rate of a discrete-time input signal with sample rate q.f s to a discrete-time output signal with a sample rate f s which is a sub multiple of the sample rate of the input signal (q=integer larger than 1), the method comprising the steps of series to parallel converting the input signal to generate non-overlapping words of q samples of the input signal and of processing said words at the sub multiple rate f s in accordance with a recursive algorithm comprising a low-pass filtering function, characterized in that the algorithm is based on a power-series expansion of the impulse-response of the low-pass filtering function.

2. A method of converting the sample rate of a discrete-time input signal with sample rate f s to a discrete-time output signal with a sample rate q.f s which is a multiple of the sample rate of the input signal (q=integer larger than 1), the method comprising the steps of processing said input signal at the sample rate f s in accordance with a recursive algorithm comprising a low-pass filtering function to obtain non-overlapping words of q samples of the output signal and of parallel to series converting said words to generate the discrete-time q.f s sample rate output signal, characterized in that the algorithm is based on a power-series expansion of the impulse-response of the low-pass filtering function.

3. An apparatus for sample rate conversion for converting the sample rate of a discrete-time input signal with sample rate q.f s to a discrete-time output signal with a sample rate f s which is a sub multiple of the sample rate of the input signal (q=integer larger than 1), comprising:

means for series to parallel converting the input signal to generate non-overlapping words of q samples of the input signal;

means for processing said words at the sub multiple rate f s in accordance with a recursive algorithm comprising a low-pass filtering function, characterized in that the algorithm is based on a power-series expansion of the impulse-response of the low-pass filtering function, said means for processing comprising a number of integrators in cascade.

4. The apparatus of claim 3 , characterized in that the low pass filtering function is of predetermined order and that the number of integrators in said cascade of integrators is one less than the said predetermined order.

5. The apparatus as claimed in claim 3 characterized in that at least one of said integrators comprises a clipper.

6. An apparatus for converting the sample rate of a discrete-time input signal with sample rate f s to a discrete-time output signal with a sample rate q.f s which is a multiple of the sample rate of the input signal (q=integer larger than 1), comprising:

means comprising a number of integrators in cascade for processing said input signal at the sample rate f s in accordance with a recursive algorithm comprising a low-pass filtering function to obtain non-overlapping words of q samples of the output signal, wherein the algorithm is based on a power-series expansion of the impulse-response of the low-pass filtering function; and

means for parallel to series converting said words to generate the discrete-time q.f s sample rate output signal; and

receiving a mapper input signal from said integrators in cascade and generating said non-overlapping words of q samples of the output signal.

7. The apparatus as claimed in claim 6 , characterized in that said mapper comprises a cascade of quantizer-subtracter combinations, each of said combinations comprising a 1-bit quantizer for generating one of the bits of said non-overlapping words of q bits and a subtracter for subtracting the input- and output-signals of the 1-bit quantizer, that the first of said combinations in the cascade receives the mapper input signal, that each of the other of said combinations in the cascade receives a weighed sum of the output signals of the subtracters of the previous combinations in the cascade and that a final quantizer receives a weighed sum of the output signals of all subtracters in the cascade and generates the final bit of said non overlapping words of q bits.