Digital clock generator
View Patent ↗The invention relates to a clock generator comprised of a system clock input ( 2 ) for applying a high-frequency system clock signal, of a digital input ( 3 ) for applying a settable digital increment value, of an adder ( 6 ) for adding the increment value with the feedback digital cumulative value of the adder, of an output register ( 13 ) for outputting the highest-order data bit of the digital cumulative value as an output clock signal of the clock generator ( 1 ) over an output clock line, and of a digital phase deviation calculating unit ( 30 ) for calculating the phase deviation of the output clock signal according to the remaining low-order data bits of the digital cumulative value and of the digital increment value, whereby the phase deviation is output as a digital phase deviation value to a digital data output ( 29 ).
1. A digital clock generator, comprising:
a system clock input to apply a high-frequency system clock signal;
a digital data input to apply an adjustable digital incremental value;
an adder to add said adjustable digital incremental value to feedback digital summed value of the adder, and provide a digital summed value indicative thereof;
an output register to output the most-significant data bit of the digital summed value as the output clock signal of the clock generator through an output clock line; and
a digital phase deviation calculation unit to calculate the phase deviation of the output clock signal as a function of the low-order data bits of the digital summed value and of the digital incremental value, wherein the phase deviation is output as a digital phase deviation value to a digital data output.
2. The digital clock generator of claim 1 , wherein the digital phase deviation calculation unit has a scaling device connected to the digital data input to scale the phase deviation value as a function of the incremental value.
3. The digital clock generator of claim 2 , wherein a scaled incremental value supplied by the scaling unit is temporarily stored in a scaling register of the digital phase deviation calculation unit.
4. The digital clock generator of claim 1 , wherein the digital phase deviation calculation unit has a register to temporarily store the low-order data bits of the digital summed value generated by the adder.
5. The digital clock generator of claim 4 , wherein the digital phase deviation calculation unit has a multi-bit multiplier which multiplies the temporarily stored scaled incremental value by the temporarily stored low-order data bit of the summed value to calculate the digital phase deviation value.
6. The digital clock generator of claim 1 , comprising a register connected following the adder to temporarily store the summed value.
7. The digital clock generator of claim 6 , wherein said register is clocked by the high-frequency system clock signal.
8. The digital clock generator of claim 7 , wherein the high-frequency system clock signal has a frequency greater than 600 MHz.
9. The digital clock generator of claim 1 , wherein the output clock line and the digital data output are connected to a data processing unit which converts an input data stream applied in an equidistant time pattern, said data stream corresponding to a sampled analog signal, to an output data stream which has the non-equidistant time pattern of the output clock signal applied to the output clock line.
10. The digital clock generator of claim 9 , comprising a digital-to-analog converter to convert the output data stream to an analog output signal.
11. The digital clock generator of claim 10 , wherein the digital-to-analog converter is clocked by the output clock signal.