Voltage buffer for capacitive loads
View Patent ↗A voltage buffer for capacitive loads isolates the load from the feedback loop. Using a variation of a follower arrangement, a second transistor outside of the feedback loop introduced. The current to the load is supplied through the second transistor, which is connected to have the same control gate level as the transistor in the feedback loop and provide an output voltage based on the reference input voltage. The output voltage is dependent upon the input voltage, but the load is removed from the feedback loop. By removing the load from the feedback loop, the loop is stabilized with only a very small or no compensating capacitor, allowing the quiescent current of the buffer to be reduced and the settling time to be improved. One preferred use of the present invention is to drive the data storage elements of a non-volatile memory.
1. A circuit to supply an output voltage from an input voltage, comprising:
a first transistor and a second transistor connected in parallel between a first of a voltage source and a reference voltage and, through a current limiting circuit, a second of the voltage source and the reference voltage; and
a differential gain stage having a first input connected to receive the input voltage, a second input connected to a node between the first transistor and the current limiting circuit, and an output connected to the control gate of the first and second transistors, wherein the output voltage is supplied from a node between the second transistor and the current limiting circuit, wherein the reference voltage is ground and said first and second transistors are NMOS transistors connected through the current limiting circuit to ground, and wherein said current limiting circuit is a current mirror comprising a third NMOS transistor and a fourth NMOS transistor whose control gates are connected, wherein the first transistor is connected to ground through the third transistor and the second transistor is connected to ground through the fourth transistor.
2. The circuit of claim 1 , wherein said circuit is of unity gain.
3. The circuit of claim 1 , wherein the second transistor has a channel width channel width approximately ten times the channel width of the first transistor.
4. A circuit to supply a set of output voltages from a respective set of input voltage, comprising:
a plurality of N first transistors connected in series between a first of a voltage source and a reference voltage and, through a current limiting circuit, a second of the voltage source and the reference voltage;
a plurality of N second transistors connected in series and connected in parallel with the first transistors between the first of the voltage source and the reference voltage and, through said current limiting circuit, the second of thie voltage source and the reference voltage; and
a plurality of N differential gain stages each having a first input connected to receive a respective one of the input voltage, a second input connected to a node at the terminal on the current limiting circuit side of a respective one of the first transistors, and an output connected to the control gate of the respective one of the first transistors and a respective one of the second transistors, wherein the respective output voltage is supplied from a node at the terminal on the current limiting circuit side of the second transistor.
5. The circuit of claim 4 , wherein said current limiting circuit is a current mirror comprising a third NMOS transistor and a fourth NMOS transistor whose control gates are connected, wherein the first transistor is connected to ground through the third transistor and the second transistor is connected to ground through the fourth transistor.
6. A circuit to supply a set of output voltages from a respective set of input voltage, comprising:
a plurality of N first transistors connected in series between a first of a voltage source and a reference voltage and, through a current limiting circuit, a second of the voltage source and the reference voltage;
a plurality of N second transistors connected in series and connected in parallel with the first transistors between the first of the voltage source and the reference voltage and, through said current limiting circuit, the second of the voltage source and the reference voltage; and
a plurality of N differential gain stages each having a first input connected to receive a respective one of the input voltage, a second input connected to a node at the terminal on the current limiting circuits side of a respective one of the first transistors, and an output connected to the control gate of the respective one of the first transistors and a respective one of the second transistors, wherein the respective output voltage is supplied from a node at the terminal on the current limiting circuit side of the second transistor.
7. The circuit of claim 6 , wherein said circuit is of unity gain.
8. The circuit of claim 6 , wherein the first of the voltage source and the reference voltage is the reference voltage, the reference voltage is ground and the second of the voltage source and the reference voltage is the voltage source, and wherein said first and second transistors are PMOS transistors.
9. The circuit of claim 6 , wherein the second transistors have a channel width channel width approximately ten times the channel width of the first transistors.