Line driver with reduced power consumption
View Patent ↗A means for reducing the power consumption of the transmitter by storing the recent history of the transmitted data using a string of gates with taps from the string taken at points determined by the propagation delay of each gate and controlling driving transistors as a function of comparison of that history with input data so that, either the signal is driven into the transmission line at full strength, or at a level near the minimum needed to retain the state in the receiver. The advantage of the invention is that the line capacitance decays through the terminating resistors or discharge transistors, such that when the next state change is needed, then line has less stored energy needing to be discharged.
1. A high speed data transmission system comprising a chip having a transmitter with a set of driving transistors for driving a signal representing transmitted data into a communication line connecting the transmitter and a receiver, the transmitter comprising:
a means for reducing the power consumption of the transmitter, including:
a means for storing the recent history of the transmitted data;
a controlling means for switching on/off the set of driving transistors as a function of comparison of that history in a logic means with data at the input of the transmitter; and
a set of keeper transistors for driving the signal into the transmission line at a level near the minimum needed to retain the state in the receiver;
wherein the means for storing the recent history of the transmission line comprises a string of gates with taps from the string taken at points determined by the propagation delay of each gate.
2. The system according to claim 1 , wherein the number of taps, delay time therebetween and a form of a logic function for converting signals from these taps to the controlling means are determined by simulation process.
3. The system according to claim 1 , wherein the controlling means comprises an inverter.
4. The system according to claim 1 , wherein the logic means comprises a comparator.
5. The system according to claim 1 wherein the logic function is implemented as a look-up table.
6. The system according to claim 1 , wherein the gates and the logic function are scaled to act as a predriver.
7. The system according to claim 1 , wherein the controlling means comprises additional transistors in the driver forming an AND or NAND function with the driving transistors.
8. The system according to claim 7 wherein the controlling means is applied to the predriver.
9. The system according to claim 1 , wherein the set of keeper transistors are sized according to termination resistors in the transmission line, such that the signal level is close to the voltage threshold of the receiver plus or minus a noise margin.
10. The system according to claim 1 , wherein the transmission line comprises a capacitive load.
11. The system according to claim 1 , wherein the transmitter comprises differential drivers.
12. A method of reducing the power consumption of a transmitter in a high speed communication system comprising a chip having the transmitter with a set of driving transistors for driving a signal representing transmitted data into a communication line connecting the transmitter and a receiver arranged on another chip,
the method comprising the steps of:
storing the recent history of the transmitted data;
comparing the history of the transmitted data with data at the input of the transmitter to enable one of the following steps:
changing the V-I characteristic of the transmitter to increase the output current of the transmitter to change the transmission line state in a required time interval; or,
changing the V-I characteristic of the transmitter to maintain the transmission line state at a level sufficient only to maintain the state of the receiver, wherein the recent history of the transmitted data is stored using a string of gates with taps from the string taken at points determined by the propagation delay of each gate,
wherein the V-I characteristic of the transmitter is changed by varying the number of switched on transistors at the output of the driver.
13. A method of reducing the power consumption of a transmitter in a high speed communication system comprising a chip having the transmitter with a set of driving transistors for driving a signal representing transmitted data into a communication line connecting the transmitter and a receiver arranged on another chip,
the method comprising the steps of:
storing the recent history of the transmitted data;
comparing the history of the transmitted data with data at the input of the transmitter to enable one of the following steps:
changing the V-I characteristic of the transmitter to increase the output current of the transmitter to change the transmission line state in a required time interval; or,
changing the V-I characteristic of the transmitter to maintain the transmission line state at a level sufficient only to maintain the state of the receiver, wherein the recent history of the transmitted data is stored using a string of gates with taps from the string taken at points determined by the propagation delay of each gate,
wherein the V-I characteristic of the transmitter is changed by varying the number of delays in the means for storing the recent history of the transmitted data.
14. A method of reducing the power consumption of a transmitter in a high speed communication system comprising a chip having the transmitter with a set of driving transistors for driving a signal representing transmitted data into a communication line connecting the transmitter and a receiver arranged on another chip,
the method comprising the steps of:
storing the recent history of the transmitted data;
comparing the history of the transmitted data with data at the input of the transmitter to enable one of the following steps:
changing the V-I characteristic of the transmitter to increase the output current of the transmitter to change the transmission line state in a required time interval; or,
changing the V-I characteristic of the transmitter to maintain the transmission line state at a level sufficient only to maintain the state of the receiver, wherein the recent history of the transmitted data is stored using a string of gates with taps from the string taken at points determined by the propagation delay of each gate,
wherein the V-I characteristic of the transmitter is changed by varying the position and number of type of taps in the means for storing the recent history of the transmitted data.
15. A means for reducing the power consumption of a transmitter in a high speed communication system comprising a chip having the transmitter with a set of driving transistors for driving a signal representing transmitted data into a communication line connecting the transmitter and a receiver arranged on another chip, the means for reducing the power consumption of the transmitter
comprising:
a means for storing the recent history of the transmitted data;
a controlling means for switching on/off the set of driving transistors as a function of comparison of that history in a logic means with data at the input of the transmitter and
a set of keeper transistors for driving the signal into the transmission line at a level near the minimum needed to retain the state in the receiver,
wherein the means for storing the recent history of the transmission line comprises a string of gates with taps from the string taken at points determined by the propagation delay of each gate.
16. The means according to claim 15 , wherein the number of taps, delay time therebetween and a logic function for converting signals from these taps to the controlling means are determined by simulation process.
17. The means according to claim 16 , wherein the simulation process is SPICE model simulation.
18. The system according to claim 2 , wherein the simulation process is SPICE model simulation.
19. The system according to claim 3 , wherein the controlling means comprises a set of inverters.
20. The system according to claim 4 , wherein the comparator is an XOR.