Reference voltage source circuit operating with low voltage

1. A reference voltage source circuit comprising:

a plurality of MOS transistors having gates of the same conduction type but of different impurity concentrations and also having equal temperature characteristics in threshold voltage wherein said MOS transistors are configured such that said voltage reference circuit maintains stable operation at less than about 1 volt.

2. The circuit as claimed in claim 1 , wherein:

each gate of said MOS transistors is formed by polycrystalline silicon or polycrystalline Si x Ge 1-x , where x denotes an integer number.

3. A reference voltage source circuit comprising:

a first MOS transistor and a second MOS transistor having gates of the same conduction type but of different impurity concentrations and also having equal temperature characteristics in threshold voltage; and

the difference between a work function of said first MOS transistor and a work function of said second MOS transistor is obtained as a reference voltage.

4. The circuit as claimed in claim 3 , wherein:

a drain current of said first MOS transistor and a drain current of said second MOS transistor are made equal.

5. The circuit as claimed in claim 4 , wherein:

the gates of said first MOS transistor and said second MOS transistor are formed by polycrystalline silicon or polycrystalline Si x Ge 1-x , where x denotes an integer number.

6. A reference voltage source circuit comprising:

a first MOS transistor and a second MOS transistor having gates of different impurity concentrations and also having equal temperature characteristics in threshold voltage; and

the difference between a voltage between a gate and a source of said first MOS transistor and a voltage between a gate and a source of said second MOS transistor is obtained as a reference voltage.

7. The circuit as claimed in claim 6 , wherein:

the gate of said first MOS transistor and the gate of said second MOS transistor are connected together; and

the difference between source voltage of said first MOS transistor and source voltage of said second MOS transistor is obtained as the reference voltage.

8. The circuit as claimed in claim 7 , wherein:

said first MOS transistor and said second MOS transistor are connected in parallel;

the source of said first MOS transistor is connected to the ground;

a circuit for making equal a current flowing through said first MOS transistor and a current flowing through said second MOS transistor is provided; and

the source voltage of said second MOS transistor is obtained as the reference voltage.

9. The circuit as claimed in claim 7 , wherein:

said first MOS transistor and said second MOS transistor are connected in serial; the source of said first MOS transistor is connected to the ground; and

the source voltage of said second MOS transistor is obtained as the reference voltage.

10. The circuit as claimed in claim 6 , wherein:

the source of said first MOS transistor and the source of said second MOS transistor are connected together; and

the difference between gate voltage of said first MOS transistor and gate voltage of said second MOS transistor is obtained as the reference voltage.

11. The circuit as claimed in claim 10 , wherein:

said first MOS transistor and said second MOS transistors are connected in parallel;

a circuit for making equal a current flowing through said first MOS transistor and a current flowing through said second MOS transistor is provided;

the gate of said second MOS transistor is connected to the ground;

a resistor is connected between the gate and the source of said first MOS transistor; and

the gate voltage of said first MOS transistor is obtained as the reference voltage.

12. The circuit as claimed in claim 11 , wherein:

said resistor comprises a plurality of resistors so as to be used as a voltage divider and accordingly, an arbitrary voltage can be obtained therefrom as the reference voltage.

13. The circuit as claimed in claim 12 , wherein:

said circuit further comprises a configuration enabling to adjust a resistance value of the plurality of resistors after the manufacturing.

14. The circuit as claimed in claim 6 , wherein:

the gate and the source of one of said first MOS transistor and said second MOS transistor are connected together; and

voltage between the gate and the source of the other one of said first MOS transistor and said second MOS transistor is obtained as the reference voltage.

15. The circuit as claimed in claim 14 , wherein:

the source of said second MOS transistor, which source is connected to the gate of said second MOS transistor, is further connected to a drain of said first MOS transistor;

a third n-channel MOS transistor is provided having a drain connected to a drain of said second MOS transistor, a gate connected to the source of said second MOS transistor, and a source connected to the gate of said first MOS transistor;

a resistor is connected between the gate and the source of said first MOS transistor; and

gate voltage of said first MOS transistor is obtained as the reference voltage.

16. The circuit as claimed in claim 15 , wherein:

said resistor comprises a plurality of resistors so as to be used as voltage divider and accordingly, an arbitrary voltage can be obtained therefrom as the reference voltage.

17. The circuit as claimed in claim 16 , wherein:

said circuit further comprises a configuration enabling to adjust a resistance value of the plurality of resistors after the manufacturing.

18. The circuit as claimed in claim 15 , wherein:

said first MOS transistor and said second MOS transistor comprise p-type-channel MOS transistors.

19. The circuit as claimed in claim 6 , wherein:

a drain current of said first MOS transistor and a drain current of said second MOS transistor are made equal.

20. The circuit as claimed in claim 6 , wherein:

the gates of said first MOS transistor and said second MOS transistor are formed by polycrystalline silicon or polycrystaliine Si x Ge 1-x , where x denotes an integer number.