IP Library Granted Patent US 6,839,870
Granted Patent B2
US 6,839,870 · App. 10/394,937 · Granted Jan 4, 2005

Error-correcting code interleaver

Assignee: Terayon Communications Systems, Inc.
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Quick Facts
Patent No.
US 6,839,870
App. No.
10/394,937
Granted
Jan 4, 2005
Kind
B2
Abstract

Memory may be partitioned into ever-sliding FIFOs. Each of the FIFOs may be stacked end-to-end in memory with the oldest data at the base offset and the newest at the end (or vice-virsa). Each symbol, the pointer may be incremented (modulo the set size) by an appropriate amount (typically J more than for the previous symbol). After each set, the pointers may be incremented by J more than the previous increment and the process starts over, wrapping around the memory if the end of the memory is reached. After a preset number of symbols, the process may restart from an increment of J. Alternatively, the pointers may be decremented rather than incremented. Thus, the newest symbol cannibalizes the memory position vacated by the oldest symbol in the current FIFO, causing the FIFOs to “slide”, providing for a very efficient and reliable use of memory for error-correcting code interleaving.

Claims (259)

1. A method for interleaving symbols of an error-correcting code having I symbols in a set, the method comprising:

setting a placeholder to an initial location in a memory of size

I

(

I

-

1

)

*

J

2

+

1

,

 wherein J is a delay value;

for every I symbols received:

repetitively counting from a step of 0 to a step of I−1, performing the following:

a) setting a write pointer equal to said placeholder;

b) if step is 0 , setting said placeholder equal to a read pointer;

c) if step is not 0 , advancing said placeholder step*J memory locations, wrapping around if said placeholder value would be past an end of said memory;

d) setting said read pointer equal to said placeholder;

e) reading out from a location in said memory indicated by said read pointer; and

f) writing a next of said I symbols to a location in said memory indicated by said write pointer, unless step is 0 , in which case it is bypassed.

2. The method of claim 1 , wherein said advancing said placeholder involves adding step*J to said placeholder, modulo said memory size.

3. The method of claim 1 , wherein said advancing said placeholder involves subtracting step*J from said placeholder, modulo said memory size.

4. The method of claim 1 , wherein a symbol is bypassed by transmitting it without delay.

5. A method for interleaving symbols of an error-correcting code having I symbols in a set, the method comprising:

setting a write pointer to an initial location in a memory of size

I

(

I

-

1

)

*

J

2

+

I

+

1

,

 wherein J is a delay value;

for every I symbols received:

repetitively counting from a step of 0 to a step of I−1, performing the following:

a) setting a read pointer equal to one memory location behind said write pointer, wrapping around if said read pointer would be past an end of said memory;

b) reading out from a location in said memory indicated by said read pointer;

c) writing a next of said I symbols to a location in said memory indicated by said write pointer; and

d) advancing said write pointer (step+1)*J memory locations, wrapping around if said write pointer would be past an end of said memory.

6. The method of claim 5 , wherein said advancing said write pointer involves adding step*J to said write pointer, modulo said memory size.

7. The method of claim 5 , wherein said advancing said write pointer involves subtracting step*J from said write pointer, modulo said memory size.

8. The method of claim 5 , wherein one memory location behind is equivalent to one memory location less than.

9. The method of claim 5 , wherein one memory location behind is equivalent to one memory location greater than.

10. A method for interleaving symbols of an error-correcting code having I symbols in a set, the method comprising:

setting a write pointer to an initial location in a memory of size

I

(

I

-

1

)

*

J

2

+

I

+

1

,

 wherein J is a delay value;

for every I symbols received:

repetitively counting from a step of 0 to a step of I−1, performing the following:

a) reading out from a location in said memory one memory location behind said write pointer, wrapping around if said location would be past an end of said memory;

c) writing a next of said I symbols to a location in said memory indicated by said write pointer; and

d) advancing said write pointer (step+1)*J memory locations, wrapping around if said write pointer would be past an end of said memory.

11. The method of claim 10 , wherein said advancing said write pointer involves adding step*J to said write pointer, modulo said memory size.

12. The method of claim 10 , wherein said advancing said write pointer involves subtracting step*J from said write pointer, modulo said memory size.

13. The method of claim 10 , wherein one memory location behind is equivalent to one memory location less than.

14. The method of claim 10 , wherein one memory location behind is equivalent to one memory location greater than.

15. An apparatus for interleaving symbols of an error correcting code having I symbols in a set, the apparatus comprising:

a memory;

a memory initializer coupled to said memory;

a placeholder setter coupled to said memory;

a step repetitive counter coupled to said placeholder setter;

a write pointer setter coupled to said memory and to said step repetitive counter;

a read pointer setter coupled to said memory and to said step repetitive counter;

a memory location reader coupled to said memory and to said step repetitive counter; and

a symbol writer coupled to said memory and to said step repetitive counter.

16. An apparatus for interleaving symbols of an error-correcting code having I symbols in a set, the apparatus comprising:

a memory;

a memory initializer coupled to said memory;

a write pointer setter coupled to said memory;

a step repetitive counter coupled to said write pointer setter;

a read pointer setter coupled to said memory and to said step repetitive counter;

a memory location reader coupled to said memory and to said step repetative counter; and

a symbol writer coupled to said memory and to said step repetitive counter.

17. An apparatus for interleaving symbols of an error-correcting code having I symbols in a set, the apparatus comprising:

a memory;

a memory initializer coupled to said memory;

a write pointer setter coupled to said memory;

a step repetitive counter coupled to said write pointer setter;

a memory location reader coupled to said memory and to said step repetitive counter; and

a symbol writer coupled to said memory and to said step repetitive counter.

18. An apparatus for interleaving symbols of an error-correcting code having I symbols in a set, the apparatus comprising:

means for setting a placeholder to an initial location in a memory of size

I

(

I

-

1

)

*

J

2

+

1

,

 wherein J is a delay value;

for every I symbols received:

means for repetitively counting from a step of 0 to a step of I−1, performing the following:

a) setting a write pointer equal to said placeholder;

b) if step is 0 , setting said placeholder equal to a read pointer;

c) if step is not 0 , advancing said placeholder step*J memory locations, wrapping around if said placeholder value would be past an end of said memory;

d) setting said read pointer equal to said placeholder;

e) reading out from a location in said memory indicated by said read pointer; and

f) writing a next of said I symbols to a location in said memory indicated by said write pointer, unless step is 0 , in which case it is bypassed.

19. The apparatus of claim 18 , wherein said advancing said placeholder involves adding step*J to said placeholder, modulo said memory size.

20. The apparatus of claim 18 , wherein said advancing said placeholder involves subtracting step*J from said placeholder, modulo said memory size.

21. The apparatus of claim 18 , wherein a symbol is bypassed by transmitting it without delay.

22. An apparatus for interleaving symbols of an error-correcting code having I symbols in a set, the apparatus comprising:

means for setting a write pointer to an initial location in a memory of size

I

(

I

-

1

)

*

J

2

+

I

+

1

,

 wherein J is a delay value;

for every I symbols received:

means for repetitively counting from a step of 0 to a step of I−1, performing the following:

a) setting a read pointer equal to one memory location behind said write pointer, wrapping around if said read pointer would be past an end of said memory;

b) reading out from a location in said memory indicated by said read pointer;

c) writing a next of said I symbols to a location in said memory indicated by said write pointer; and

d) advancing said write pointer (step+1)*J memory locations, wrapping around if said write pointer would be past an end of said memory.

23. The apparatus of claim 22 , wherein said advancing said write pointer involves adding step*J to said write pointer, modulo said memory size.

24. The apparatus of claim 22 , wherein said advancing said write pointer involves subtracting step*J from said write pointer, modulo said memory size.

25. The apparatus of claim 22 , wherein one memory location behind is equivalent to one memory location less than.

26. The apparatus of claim 22 , wherein one memory location behind is equivalent to one memory location greater than.

27. An apparatus for interleaving symbols of an error-correcting code having I symbols in a set, the apparatus comprising:

means for setting a write pointer to an initial location in a memory of size

I

(

I

-

1

)

*

J

2

+

I

+

1

,

 wherein J is a delay value;

for every I symbols received:

means for repetitively counting from a step of 0 to a step of I−1, performing the following:

a) reading out from a location in said memory one memory location behind said write pointer, wrapping around if said location would be past an end of said memory;

c) writing a next of said I symbols to a location in said memory indicated by said write pointer; and

d) advancing said write pointer (step+1)*J memory locations, wrapping around if said write pointer would be past an end of said memory.

28. The apparatus of claim 27 , wherein said advancing said write pointer involves adding step*J to said write pointer, modulo said memory size.

29. The apparatus of claim 27 , wherein said advancing said write pointer involves subtracting step*J from said write pointer, modulo said memory size.

30. The apparatus of claim 27 , wherein one memory location behind is equivalent to one memory location less than.

31. The apparatus of claim 27 , wherein one memory location behind is equivalent to one memory location greater than.

32. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method for interleaving symbols of an error-correcting code having I symbols in a set, the method comprising:

setting a placeholder to an initial location in a memory of size

I

(

I

-

1

)

*

J

2

+

1

,

 wherein J is a delay value;

for every I symbols received:

repetitively counting from a step of 0 to a step of I−1, performing the following:

a) setting a write pointer equal to said placeholder;

b) if step is 0 , setting said placeholder equal to a read pointer;

c) if step is not 0 , advancing said placeholder step*J memory locations, wrapping around if said placeholder value would be past an end of said memory;

d) setting said read pointer equal to said placeholder;

e) reading out from a location in said memory indicated by said read pointer; and

f) writing a next of said I symbols to a location in said memory indicated by said write pointer, unless step is 0 , in which case it is bypassed.

33. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method for interleaving symbols of an error-correcting code having I symbols in a set, the method comprising:

setting a write pointer to an initial location in a memory of size

I

(

I

-

1

)

*

J

2

+

I

+

1

,

 wherein J is a delay value;

for every I symbols received:

repetitive counting from a step of 0 to a step of I−1, performing the following:

a) setting a read pointer equal to one memory location behind said write pointer, wrapping around if said read pointer would be past an end of said memory;

b) reading out from a location in said memory indicated by said read pointer;

c) writing a next of said I symbols to a location in said memory indicated by said write pointer; and

d) advancing said write pointer (step+1)*J memory locations, wrapping around if said write pointer would be past an end of said memory.

34. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method for interleaving symbols of an error-correcting code having I symbols in a set, the method comprising:

setting a write pointer to an initial location in a memory of size

I

(

I

-

1

)

*

J

2

+

I

+

1

,

 wherein J is a delay value;

for every I symbols received:

repetitively counting from a step of 0 to a step of I−1, performing the following:

a) reading out from a location in said memory one memory location behind said write pointer, wrapping around if said location would be past an end of said memory;

c) writing a next of said I symbols to a location in said memory indicated by said write pointer; and

d) advancing said write pointer (step+1)*J memory locations, wrapping around if said write pointer would be past an end of said memory.

Assignments (11)
RELEASE OF SECURITY INTEREST AT REEL/FRAME 049905/0504 Recorded Dec 19, 2024
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: ARRIS ENTERPRISES LLC (F/K/A ARRIS ENTERPRISES, INC.); ARRIS TECHNOLOGY, INC.; ARRIS SOLUTIONS, INC.; COMMSCOPE, INC. OF NORTH CAROLINA; COMMSCOPE TECHNOLOGIES LLC; RUCKUS WIRELESS, LLC (F/K/A RUCKUS WIRELESS, INC.)
Reel/Frame 071477/0255 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2022
From: ARRIS TECHNOLOGY, INC.
To: ARRIS ENTERPRISES, INC.
Reel/Frame 060791/0583 →
SECURITY INTEREST Recorded Nov 19, 2021
From: ARRIS SOLUTIONS, INC.; ARRIS ENTERPRISES LLC; COMMSCOPE TECHNOLOGIES LLC; COMMSCOPE, INC. OF NORTH CAROLINA; RUCKUS WIRELESS, INC.
To: WILMINGTON TRUST
Reel/Frame 060752/0001 →
CHANGE OF NAME Recorded Feb 4, 2020
From: ARRIS ENTERPRISES, INC.
To: ARRIS ENTERPRISES LLC
Reel/Frame 051797/0858 →
TERM LOAN SECURITY AGREEMENT Recorded Jul 3, 2019
From: COMMSCOPE, INC. OF NORTH CAROLINA; COMMSCOPE TECHNOLOGIES LLC; ARRIS ENTERPRISES LLC; ARRIS TECHNOLOGY, INC.; RUCKUS WIRELESS, INC.; ARRIS SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 049905/0504 →
PATENT SECURITY AGREEMENT Recorded Jul 3, 2019
From: ARRIS ENTERPRISES LLC
To: WILMINGTON TRUST, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 049820/0495 →
ABL SECURITY AGREEMENT Recorded Jul 3, 2019
From: COMMSCOPE, INC. OF NORTH CAROLINA; COMMSCOPE TECHNOLOGIES LLC; ARRIS ENTERPRISES LLC; ARRIS TECHNOLOGY, INC.; RUCKUS WIRELESS, INC.; ARRIS SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 049892/0396 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Apr 8, 2019
From: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
To: ARRIS GROUP, INC.; ARRIS ENTERPRISES, INC.; ARRIS SOLUTIONS, INC.; ARRIS KOREA, INC.; ARRIS HOLDINGS CORP. OF ILLINOIS, INC.; BIG BAND NETWORKS, INC.; TEXSCAN CORPORATION; POWER GUARD, INC.; 4HOME, INC.; ACADIA AIC, INC.; AEROCAST, INC.; BROADBUS TECHNOLOGIES, INC.; GENERAL INSTRUMENT CORPORATION; GENERAL INSTRUMENT AUTHORIZATION SERVICES, INC.; GENERAL INSTRUMENT INTERNATIONAL HOLDINGS, INC.; IMEDIA CORPORATION; JERROLD DC RADIO, INC.; LEAPSTONE SYSTEMS, INC.; MODULUS VIDEO, INC.; MOTOROLA WIRELINE NETWORKS, INC.; NETOPIA, INC.; NEXTLEVEL SYSTEMS (PUERTO RICO), INC.; QUANTUM BRIDGE COMMUNICATIONS, INC.; SETJAM, INC.; SUNUP DESIGN SYSTEMS, INC.; UCENTRIC SYSTEMS, INC.; GIC INTERNATIONAL HOLDCO LLC; GIC INTERNATIONAL CAPITAL LLC; CCE SOFTWARE LLC; THE GI REALTY TRUST 1996
Reel/Frame 048825/0294 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2015
From: ARRIS TECHNOLOGY, INC
To: ARRIS ENTERPRISES, INC.
Reel/Frame 037328/0341 →
SECURITY AGREEMENT Recorded May 28, 2013
From: ARRIS GROUP, INC.; ARRIS ENTERPRISES, INC.; ARRIS SOLUTIONS, INC.; ARRIS KOREA, INC.; ARRIS HOLDINGS CORP. OF ILLINOIS; BIGBAND NETWORKS, INC.; TEXSCAN CORPORATION; POWER GUARD, INC.; 4HOME, INC.; ACADIA AIC, INC.; AEROCAST, INC.; BROADBUS TECHNOLOGIES, INC.; GENERAL INSTRUMENT CORPORATION; GENERAL INSTRUMENT AUTHORIZATION SERVICES, INC.; GENERAL INSTRUMENT INTERNATIONAL HOLDINGS, INC.; IMEDIA CORPORATION; JERROLD DC RADIO, INC.; LEAPSTONE SYSTEMS, INC.; MODULUS VIDEO, INC.; MOTOROLA WIRELINE NETWORKS, INC.; NETOPIA, INC.; NEXTLEVEL SYSTEMS (PUERTO RICO), INC.; QUANTUM BRIDGE COMMUNICATIONS, INC.; SETJAM, INC.; SUNUP DESIGN SYSTEMS, INC.; UCENTRIC SYSTEMS, INC.; GIC INTERNATIONAL HOLDCO LLC; GIC INTERNATIONAL CAPITAL LLC; CCE SOFTWARE LLC; THE GI REALTY TRUST 1996
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 030498/0023 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2003
From: FANFELLE, ROBERT J.; HUBRIS, ALEX
To: TERAYON COMMUNICATIONS SYSTEMS, INC.
Reel/Frame 013905/0212 →
Continuity (1)
Related Publication 20040187063A1 · Sep 23, 2004