Independence between paths that predistort for memory and memory-less distortion in power amplifiers
View Patent ↗A predistorter for reducing spurious emissions in an amplified signal including a first path configured to generated memory-less distortion correction and one or more second paths configured to generate memory distortion correction. The paths contain one or more dynamically controllable delay circuits that are configured such that the memory-less and memory distortion correction remains independent irrespective of frequency of use of the predistorter.
1. A predistorter for reducing spurious emissions in an amplified signal comprising:
a first path configured to generate memory-less distortion correction;
a second path configured to generate memory distortion correction; and
at least one dynamically controllable delay circuit located in at least one of the first and second paths and configured to render the memory-less and memory distortion corrections independent from one another over a plurality of operating frequencies for the predistorter, wherein the first path is disposed in a first layer, and the second path is disposed in a second layer, wherein the second layer further comprises a third path, wherein the second path is a second layer long path and the third path is a second layer short path, and wherein the dynamically controllable delay circuit is configured to add a delay to the second layer long path that is an integer number of wavelengths long relative to a delay added to the second layer short path at the frequency of use of the predistorter.
2. The predistorter of claim 1 , wherein the first path is configured with the same insertion phase and delay as the second layer short path.
3. The predistorter of claim 1 , wherein the second layer long path is configured with 180 degrees of additional insertion phase but the same insertion delay as the second layer short path.
4. The predistorter of claim 1 , wherein the first path is configured with twice as much delay as the second layer long path.
5. The predistorter of claim 1 , further comprising a processor coupled to the at least one dynamically controllable delay circuit and configured to select the delay added by the dynamically controllable delay circuit.
6. The predistorter of claim 1 , further comprising a plurality of look-up tables, each associated with a path and configured to produce a correction signal that is equal but opposite in magnitude and phase to at least a portion of non-linearities associated with an RF power amplifier.
7. The predistorter of claim 6 , further comprising a processor, the processor configured to update the look-up tables based on an amplified signal.
8. The predistorter of claim 1 , further comprising a combiner configured to combine the first and second paths.
9. An apparatus comprising:
an RF amplifier configured to amplify a signal; and,
a predistorter coupled to the RF amplifier and configured to reduce spurious emissions in an amplified signal, the predistorter comprising:
a first path configured to generate memory-less distortion correction;
a second path configured to generate memory distortion correction;
at least one dynamically controllable delay circuit located in at least one of the first and second paths and configured to render the memory-less and memory distortion corrections independent from one another over a plurality of frequencies for the predistorter;
wherein the first path is disposed in a first layer, and the second path is disposed in a second layer, wherein the second layer further comprises a third path, wherein the second path is a second layer long the third path is a second layer short path, and wherein the dynamically controllable delay circuit is configured to add a delay to the second layer long path that is an integer number of wavelengths long relative to a delay added to the second layer short path at the frequency of use of the predistorter.
10. The apparatus of claim 9 , wherein the first path is configured with the same insertion phase and delay as the second layer short path.
11. The apparatus of claim 9 , wherein the second layer long path is configured with 180 degrees of additional insertion phase but the same insertion delay as the second layer short path.
12. The apparatus of claim 9 , wherein the first path is configured with twice as much delay as the second layer long path.
13. The apparatus of claim 9 , the predistorter further comprising a processor coupled to the at least one dynamically controlled delay circuit and configured to select delay.
14. The apparatus of claim 9 , the predistorter further comprising a plurality of look-up tables, each associated with a path and configured to produce a correction signal that is equal but opposite in magnitude and phase to at least a portion of non-linearities associated with the RF power amplifier.
15. The apparatus of claim 14 , wherein the look-up tables are updated based on an amplified signal.
16. The apparatus of claim 9 , wherein the predistorter further comprises a combiner configured to combine the first and second paths.
17. A method of reducing spurious emissions in an amplified signal using a predistorter wherein the predistorter includes first and second paths and at least one delay circuit located in at least one of the first and second paths, the method comprising:
correcting for memory-less distortion using the first path;
correcting for memory distortion using the second path; and,
dynamically controlling the delay circuit to render the memory-less and memory distortion corrections independent from one another over a plurality of operating frequencies for the predistorter;
wherein the first path is disposed in a first layer, and the second path is disposed in a second layer, wherein the second layer further comprises a third path, wherein the second path is a second layer long path and the third path is a second layer short path, and wherein dynamically controlling the delay circuit comprises adding delay to the second layer long path that is an integer number wavelengths long relative to delay added to the second layer short path.
18. The method of claim 17 , wherein dynamically controlling the delay circuit comprises setting the first path and the second layer short path with the same insertion phase and delay.
19. The method of claim 17 , wherein dynamically controlling the delay circuit comprises setting the second layer long path with 180 degrees of additional insertion phase but the same insertion delay as the second layer short path.
20. The method of claim 17 , wherein dynamically controlling the delay circuit comprises setting the delay of the first path with twice as much delay as the second layer long path.
21. The method of claim 17 , further comprising producing a correction signal using look-up tables that is equal but opposite in magnitude and phase to a least a portion of non-linearities associated with an RF power amplifier.
22. The method of claim 21 , further comprising updating the look-up tables based on an amplified signal.
23. The method of claim 17 , further comprising combining the first and second paths.