Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature
View Patent ↗A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules. The unload pointer increments in accordance with a clock generated by the computer system itself Because the trace length of each memory channel may differ, the time that it takes for a memory module to provide read data back to the memory controller may differ for each channel. The “skew” is defined as the difference in time between when the data arrives on the earliest channel and when data arrives on the latest channel. During system initialization, the pointers are synchronized. After initialization, the pointers are used to load and unload the read buffers in such a way that the effects of inner-channel skew is eliminated.
1. A memory controller, comprising:
a plurality of multi-entry read buffers each coupled to a memory module, data from said memory modules being stored in said read buffers in response to a read command;
a plurality of load pointer logic circuits each generating a load pointer that identifies an entry in an associated read buffer in which data is to be loaded;
a plurality of unload pointer logic circuits each generating an unload pointer that identifies an entry in an associated read buffer from which data is to be consumed;
each of said load pointer logic circuits and said unload pointer logic circuits receiving a synch arm signal which causes said logic circuits to hold their associated pointers at a predetermined pointer value to initialize the pointers; and
wherein during initialization all of said unload pointer logic circuits receive a read strobe signal that causes the unload pointer logic circuits to release their unload pointers to begin incrementing, and a clock signal to increment the unload pointers.
2. The memory controller at claim 1 each unload pointer logic circuit increments its unload pointer using a clock signal provided from a dock divider coupled to the unload pointer logic circuit.
3. The memory controller of claim 1 wherein all of said load pointer logic circuits couple to a data bus which couples to at least some of the memory modules and during initialization when each of said load pointer logic circuits detects the presence of a bit pattern on its associated data bus causes its load pointer to be released and begin incrementing.
4. The memory controller of claim 1 wherein, after initialization completes, said load and unload pointers are free running pointers.
5. The memory controller of claim 1 wherein, after initialization, said load pointer logic circuits increment their load pointers using source synchronous clocking.
6. The memory controller of claim 5 wherein, after initialization, said unload pointer logic circuits increment their unload pointers using a clock that is not guaranteed to be substantially in phase with clocks used by the load pointer logic circuits to increment the load pointers.
7. A computer system, comprising:
a CPU core;
an I/O device coupled to said CPU core; and
a memory controller coupled to a plurality of memory modules, comprising
a plurality of multi-entry read buffers each coupled to a memory module, data from said memory modules being stored in said read buffers in response to a read command;
a plurality of load pointer logic circuits each generating a load pointer that identifies an entry in an associated read buffer in which data is to be loaded;
a plurality of unload pointer logic circuits each generating an unload pointer that identifies an entry in an associated read buffer from which data is to be consumed; and
each of said load pointer logic circuits and said unload pointer logic circuits receiving a synch arm signal which causes said logic circuits to hold their associated pointers at a predetermined pointer value to initialize the pointers;
wherein during initialization all of said unload pointer logic circuits receive a read strobe signal that causes the unload pointer logic circuits to release their unload pointers to begin incrementing, and a clock signal to increment the unload pointers.
8. The computer system of claim 7 each unload pointer logic circuit increments its unload pointer using a dock signal provided from a clock divider coupled to the unload pointer logic circuit.
9. The computer system of claim 7 wherein all of said load pointer logic circuits couple to a data bus which couples to at least some of the memory modules and during initialization when each of said load pointer logic circuits detects the presence of a bit pattern on its associated data bus causes its load pointer to be released and begin incrementing.
10. The computer system of claim 7 wherein, after initialization completes, said load and unload pointers are free running pointers.
11. The computer system of claim 7 wherein, after initialization, said load pointer logic circuits increment their load pointers using source synchronous clocking.
12. The computer system of claim 11 wherein, after initialization, said unload pointer logic circuits increment their unload painters using a clock that is not guaranteed to be substantially in phase with clocks used by the load pointer logic circuits to increment the load pointers.