Communication bus system
View Patent ↗The bus controller of a bus system supports isochronous messages and non-isochronous messages for which the bus system does and does not support a guaranteed transceiving capacity per time-frame respectively. The system has a first and second memory section for exchange of data from the isochronous messages between a processor and the bus controller. The bus controller has access priority over the processor in alternating first and second ones of the time frames. The bus controller transfers data from isochronous messages between the bus medium and the first and second memory section in the first and second ones of the time frames respectively. The processor has access priority to the first and second memory section over the bus controller in the second and first ones of the time frames respectively. The system contains a third memory section for exchange of data from the non-isochronous messages, a relative access priority of the processor and bus-controller to the third memory section being unchanged in all time frames.
1. A communication bus system comprising:
a bus medium ( 16 );
a bus controller ( 120 ) that is arranged to transmit and/or receive messages via the bus medium ( 16 ) in successive time frames, the bus controller ( 120 ) supporting isochronous messages and non-isochronous messages for which the bus system does and does not support a guaranteed transceiving capacity per time-frame respectively;
a processor ( 10 );
a first and second memory section ( 122 a,b ) for exchange of data from the isochronous messages between the processor ( 10 ) and the bus controller ( 120 ), the bus system being arranged to give the bus controller ( 120 ) access priority over the processor ( 10 ) in first and second ones of the time frames respectively, the first and second ones of the time-frames alternating with one another, the bus controller ( 120 ) transferring data from isochronous messages between the bus medium ( 16 ) and the first and second memory section ( 122 a,b ) in the first and second ones of the time frames respectively, the processor ( 10 ) having access priority to the first and second memory section ( 122 a, b ) over the bus controller ( 120 ) in the second and first ones of the time frames respectively;
a third memory section ( 14 ) for exchange of data from the non-isochronous messages, a relative access priority of the processor ( 10 ) and bus-controller ( 120 ) to the third memory section ( 14 ) being unchanged in all time frames.
2. A communication bus system according to claim 1 , wherein the bus controller ( 120 ) has an interrupt output and the processor ( 10 ) has an interrupt input coupled to the interrupt output, the bus controller ( 120 ) being arranged to send an interrupt to the processor ( 10 ) upon completion of data transfer using the first and second memory section ( 122 a,b ) in the first and second time frames respectively.
3. A communication bus system according to claim 2 , wherein the bus controller ( 120 ) is arranged to transfer the data between the bus medium ( 16 ) and the first or second memory section ( 122 a,b ) in each time frame before transferring data between the bus medium ( 16 ) and the third memory section ( 14 ), the bus controller ( 160 ) being arranged to send a further interrupt upon completion of data transfer using the third memory section ( 14 ) in each time frame.
4. A communication bus system according to claim 3 , wherein the processor ( 10 ) is programmed to start reading or writing the data in the first and second memory section ( 122 a,b ) in response to the interrupt in the first and second time frame respectively.
5. A communication bus interface circuit ( 12 ) comprising:
an interface for connecting a bus medium ( 16 );
a bus controller ( 120 ) that is arranged to transmit and/or receive messages via the interface in successive time frames, the bus controller ( 120 ) supporting isochronous messages and non-isochronous messages for which the bus interface circuit does and does not support a guaranteed transceiving capacity per time-frame respectively,
an interface for a processor ( 10 );
a first and second memory section ( 122 a,b ) for exchange of data from the isochronous messages between the processor ( 10 ) and the bus controller ( 120 ), the bus interface circuit ( 12 ) being arranged to give the bus controller ( 120 ) access priority over the processor ( 10 ) in first and second ones of the time frames respectively, the first and second ones of the time frames alternating with one another, the bus controller ( 120 ) transferring data from isochronous messages between the interface for the bus medium ( 16 ) and the first and second memory section ( 122 a,b ) in the first and second ones of the time frames respectively, the interface for the processor having access priority to the first and second memory section ( 122 a,b ) over the bus controller ( 120 ) in the second and first ones of the time frames respectively;
an interface to a third memory section ( 14 ) for exchange of data from the non-isochronous messages, a relative access priority of the interface for the processor ( 10 ) and bus-controller ( 120 ) to the third memory section being unchanged in all time frames.