Testing of circuit with plural clock domains
View Patent ↗An electronic circuit has a plurality of sub-circuits. Clock gate circuits supply gated clock signals to data storage elements of the sub-circuits. The clock gate circuits have gate inputs for receiving gate signals that commands blocking passage of the clock signal. Data can be transferred between data storage elements between two of the subcircuits. A detector circuit flags invalid data in the data storage element of the second one of the sub-circuits. The detector circuit has a flag storage element arranged to set a flag when the clock gate circuit of the second one of the sub-circuits passes the clock signal for the second one of the sub-circuits after the clock gate of the first one of the sub-circuits has blocked the clock signal for the first one of the sub-circuits. The flag indicates the relative phase of the clocks signals of different sub-circuits when the clocks are stopped. The flag is used to invalidate data in the data storage element of the second one of the sub-circuits.
1. An electronic circuit comprising:
clock circuitry;
a first sub-circuit comprising a first clocked data storage element and a first clock gate circuit that is coupled between an output of the clock circuitry and a clock input of the first data storage element;
a second sub-circuit comprising a second data storage element, within a different clock domain as the first data storage element, and a second clock gate circuit that is coupled between an output of the clock circuitry and a clock input of the second data storage element;
a data path between the first clocked storage element and the second clocked storage element;
a detector circuit, coupled between the first sub-circuit and the second sub-circuit, that flags an invalid data write operation in the second data storage element in relation to the first clocked gate circuit receiving a gate signal that commands blocking passage of a first clock signal from the clock circuitry.
2. The electronic circuit of claim 1 wherein the detector circuit comprises:
a pre-flag storage element that sets a pre-flag in response to the first clock signal from the clock circuitry being blocked; and
a first flag storage element that copies the pre-flag in response to the second clock gate circuit passing a second clock signal for the second sub-circuit.
3. The electronic circuit of claim 2 further comprising:
a third sub-circuit comprising, a third clocked data storage element and a third clock gate circuit, that is coupled to receive data from the first clocked data storage element; and
wherein the detector circuit further comprises a second flag storage element that copies the pre-flag in response to the third clock gate circuit passing a third clock signal for the third sub-circuit.
4. The electronic circuit of claim 1 further comprising a pipeline storage element coupled to the second clocked data storage element for copying data from the second clocked data storage element to preserve erroneously overwritten in the second clocked data storage element.
5. The electronic circuit of claim 4 comprising an output circuit for reading data from the second clocked data storage element and the pipeline storage element in response to a flag not being appropriately set.
6. The electronic circuit of claim 1 further comprising a scan chain, coupled to a flag storage element and the second clocked data storage element, that allows a flag and data from the second data storage element to be read.
7. A method of testing an electronic circuit containing a plurality of clocked data storage elements, the method comprising:
operating a first clocked data storage element, within the plurality of clocked data storage elements, in a first clock domain;
operating a second clocked data storage element, within the plurality of clocked data storage elements, in a second clock domain that is different than the first clock domain;
commanding a plurality of clock gate circuits, associated with the plurality of clocked data storage elements, to block passage of at least one clock signal;
detecting a write error at the second clocked data storage element caused by the command to block passage of at least one clock signal; and
correcting the write error at the second clocked data storage element.
8. The method of claim 7 wherein the write error is detected by removing a flag in response to a complete write operation by the second clocked data storage element.